hd66740 Renesas Electronics Corporation., hd66740 Datasheet
hd66740
Related parts for hd66740
hd66740 Summary of contents
Page 1
... It fixed-displays a part of the graphics icons so that the user can easily see a variety of information. The HD66740 has various functions to reduce the power consumption of an LCD system such as low- voltage operation of 1.8 V min., a booster to generate maximum five-times LCD drive voltage from the supplied voltage, and voltage-followers to decrease the direct current flow in the LCD drive bleeder- resistors ...
Page 2
... HD66740 Vertical smooth scroll Partial smooth scroll control (fixed display of graphics icons) Vertical double-height display by each display line Black-and-white reversed display Wide range of instruction functions: Display on/off control, black-and-white reversed No wait time for instruction execution and RAM access Internal oscillation and hardware reset ...
Page 3
... Five-times (135 µA) Bus Interface 4/8-bits parallel and clock synchronized serial 4/8-bits parallel and I2C bus interface 4/8-bits parallel and clock synchronized serial 4/8-bits parallel and I2C bus interface 3 HD66740 <Target values> Sleep Standby Mode Mode (15 µA) 0.1 µA (15 µA) (15 µA) (15 µ ...
Page 4
... V to 5 3 — I2C bus interface (HD66740W) Clock-synchronized serial Clock-synchronized serial 4 bits, 8 bits 4 bits, 8 bits Impossible Impossible 1/8, 16, 24, 32, 40, 48, 56, 64 1/8, 16, 24, 32, 40, 48, 56, 64 72, 80 72, 80 1/4 to 1/10 1 ...
Page 5
... HD66740 Block Diagram RESET* TEST Instruction register (IR) 8 IM2-1 IM0/ID CS* System interface RS - Clock synchro- E/WR*/SCL nized 8 serial Data RW/RD*/SDA - I2C bus register (DR) - 4-bit bus - 8-bit bus DB0-DB7 generator RAM Vci C1+ C1- C2+ Triple to C2- five-times C3+ Parallel/serial converter booster C3- C4+ C4- VLOUT Contrast adjuster Vcc VTEST1— ...
Page 6
... HD66740 HD66740 Pad Arrangement - Chip size : 9.40mm x 2.18mm - Chip thickness : 550um (typ.) - PAD coordinates : PAD center - Coodinate origin : Chip center - Au bump size (pin number is shown in the blacket) (1)80um x 80um Dummy1(1) to Dummy2(78), Dummy3(104), Dummy20(263) (2)45um x 80um COM34(105) to COM80(119) Dummy4(120) Dummy5(121) to Dummy10(126) Dummy13(241) to Dummy18(246) ...
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... HD66740 Pad Coordinate No. PAD NAME X Y No. PAD NAME 1 DUMMY1 -4538 -930 73 V5OUT 2 GNDDUM -4336 -930 74 VTEST1 3 IM2 -4190 -930 75 VTEST2 4 IM1 -4045 -930 76 VTEST3 5 IM0/ID -3915 -930 77 GNDDUM2 6 VCCDUM -3813 -930 78 DUMMY2 7 OPOFF -3711 -930 79 COM9/72 8 TEST -3609 -930 80 COM10/71 9 DB7 ...
Page 8
... HD66740 TCP Dimensions (HD66740TB0) IM2 IM1 IM0/ID OPOFF TEST DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RESET* CS* I/O, Power supply RS E/WR*/SCL RW/RD*/SDA GND 0.65P x (49 – 1) OSC2 OSC1 = 31.20 mm Vcc Vci C4+ C4- C3+ C3- C2+ C2- C1+ C1- VLOUT VLCD V1OUT ...
Page 9
... Inputs the ID of the device ID code for a serial bus and I2C bus interface. Selects the HD66740: Low: HD66740 is selected and can be accessed High: HD66740 is not selected and cannot be accessed Must be fixed at GND level when not in use. Selects the register for a parallel bus interface. ...
Page 10
... HD66740 Table 2 Pin Functional Description (cont) Number of Signals Pins I/O Connected to DB0–DB7 8 I/O or MPU I COM1/80– LCD COM80/1 SEG1/112– 112 O LCD SEG112/1 V1OUT– Open or OUT external bleeder-resistor V 3 — Power supply LCD V , GND 12 — Power supply ...
Page 11
... This signal enters the normal drive mode or high-power mode in the GND side according to the VTEST1 pin setting, and it enters the low-power drive mode in the V in the low-power mode so that the display quality is no lowered. 11 HD66740 ), level; shorting this pin sets the level. CC side. ...
Page 12
... HD66740 Block Function Description System Interface The HD66740 has six types of system interfaces, and a clock-synchronized serial, an I2C bus interface, a 68-system 4-bit/8-bit bus, and a 80-system 4-bit/8-bit bus. The interface mode is selected by the IM2-0 pins. The HD66740 has two 8-bit registers: an instruction register (IR) and a data register (DR). ...
Page 13
... Oscillation Circuit (OSC) The HD66740 can provide R-C oscillation simply through the addition of an external oscillation-resistor between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also be supplied externally ...
Page 14
... HD66740 CGRAM Address Map Table 4 Relationship between Display Position and CGRAM Address (1) Segment Driver SGS="0" 000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 SGS="1" 06F 06E 06D 06C 06B 06A 069 068 067 066 065 064 063 062 061 060 05F ...
Page 15
... HD66740 Segment Common 2EB 2EC 2ED 2EE 2EF (HEX) 284 283 282 281 280 COM41 COM42 COM43 ...
Page 16
... HD66740 Instructions Outline Only the instruction register (IR) and the data register (DR) of the HD66740 can be controlled by the MPU. Before starting internal operation of the HD66740, control information is temporarily stored in these registers to allow interfacing with various peripheral control devices or MPUs which operate at different speeds. The internal operation of the HD66740 is determined by signals sent from the MPU. ...
Page 17
... SEG1, and SEG112/1 to SEG112. When SGS = "1", SEG1/112 shifts SEG112, and SEG112/1 to SEG1. R/W RS DB7 Figure 2 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Start Oscillation Instruction DB6 DB5 DB4 DB3 DB2 DB1 DB0 CMS SGS Driver Output Control Instruction 17 HD66740 ...
Page 18
... AMP = 0, current consumption can be reduced while the display is not being used. SLP: When SLP = 1, the HD66740 enters the sleep mode, where the internal operations are halted except for the R-C oscillator, thus reducing current consumption. For details, see the Sleep Mode section. Only the power control (AMP, SLP, and STB bits) instruction can be executed during the sleep mode ...
Page 19
... DB6 DB5 DB4 DB3 DB2 DB1 Figure 4 V GND Figure 5 DB0 CT4 CT3 ( ( BT1 BT0 CT2 CT1 CT0 ( ( BS2 BS1 BS0 Contrast-Control 1/2 Instruction HD66740 LCD GND Contrast Adjuster 19 HD66740 ...
Page 20
... HD66740 Table 6 CT Bits and Variable Resistor Value of Contrast Adjuster CT Set Value CT5 CT4 CT3 CT2 • • • • ...
Page 21
... Table 8 BS Bits and LCD Drive Bias Value BS2 BS1 BS0 Liquid Crystal Display Drive Bias Value 1/10 bias drive 1/9.5 bias drive 1/9 bias drive 1/8 bias drive 1/7 bias drive 1/6 bias drive 1/5 bias drive 1/4 bias drive 21 HD66740 ...
Page 22
... HD66740 Entry Mode REV: Displays all graphics display sections with black-and-white reversal when and REV = 1. For details, see the Reversed Display Function section. I/D: When increments (I decrements (I the CGRAM address by 1 when a data is written into or read from the CGRAM. ...
Page 23
... DDRAM or CGRAM, and can be displayed instantly by setting When the display is off with the SEG1 to SEG112 outputs and COM1 to COM80 outputs set to the GND level. Because of this, the HD66740 can control charging current for the LCD with AC driving. DL10: When DL10 can be set. When DL10 = 1, the 10th line is displayed at double height. ...
Page 24
... HD66740 Display Line Control NL3-0: Set NL2–NL0 bits when and the NL3 bit when specify the display lines. Display lines change the liquid crystal display drive duty ratio. depend on the number of display lines. R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 ...
Page 25
... COM73 COM80 COM57 COM72 COM1 • • COM2 • • COM63 COM66 COM64 COM65 COM8 Specify the double-height display for any line. When DL1 = 25 HD66740 CMS = 1 COM8 COM7 • • • • COM2 COM1 COM80 COM79 • • • • COM73 ...
Page 26
... HD66740 height. When DL3 = 1, the third line is displayed at double height. Double-height display of multiple lines is possible. For details, see the Double-height Display section. DL6-4: Can be specified when the fourth line is displayed at double height. When DL5 = 1, the fifth line is displayed at double height. When DL6 = 1, the sixth line is displayed at double height. For the seventh to 10th lines, control double-height display by using the DL7– ...
Page 27
... SN3 ( SL2 SL1 SL0 ( <0> PS1 PS0 ( Vertical Scroll Control 1/2 Instruction Display-start Line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 27 HD66740 Specify the display start ...
Page 28
... HD66740 Table 12 SL Bits and Display-start Raster-row SL2 SL1 SL0 Display-start Raster-row 1st raster-row 2nd raster-row 3rd raster-row 4th raster-row 5th raster-row 6th raster-row 7th raster-row 8th raster-row PS1–0: Specify PS1 to PS0 bits when ...
Page 29
... R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 NW2 EOR Figure 11 LCD-Driving-Waveform Control Instruction 29 HD66740 DB0 NW1 NW0 ( ( NW4 NW3 ...
Page 30
... HD66740 RAM Address Set AD10-0: Initially set RAM addresses to the address counter (AC). Once the RAM data is written, the AC is automatically updated according to the I/D bit. This allows consecutive accesses without resetting addresses. Once the RAM data is read, the AC is automatically updated according to the I/D bit when RDM = 0, and not updated when RDM = 1 ...
Page 31
... Read Data from RAM Instruction Address: N set First byte Dummy read (invalid data) Second byte Dummy read (invalid data) Third byte Read (data of address N) Address (RDM = 0) Address: N (RDM = 1) ii) Serial interface mode RAM Read Sequence 31 HD66740 Start byte Start byte ...
Page 32
... HD66740 Table 14 Instruction List Register Name R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Start oscillation Driver output control Power control Contrast control Contrast control Entry mode set ...
Page 33
... SN2 SN1 SN0 Sets the display-start line (SN2-0). <0> <0> SN3 Sets the display-start line (SN3 SL2 SL1 SL0 Sets the display-start raster- row (SL2-0). <0> PS1 PS0 Sets the partial scroll (PS1–0). 33 HD66740 Execu- tion Cycle ...
Page 34
... HD66740 Table 14 Instruction List (cont) Register Name R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description LCD-driving pattern control LCD-driving waveform control RAM address set (upper bits) RAM address set (lower bits) Write data to RAM 0 ...
Page 35
... B C-pattern waveform drive EOR = 1: EOR alternating drive at C-pattern waveform NW4–0: Reversed number of n raster-rows at C-pattern waveform drive (alternating with the set value + one raster-row) DCC = 0: Boosted at 1/64-divided clock DCC = 1: Boosted at 1/32-divided clock AD10-0: CGRAM address set (CGRAM: 000H-4EFH) HD66740 35 ...
Page 36
... HD66740 Reset Function The HD66740 is internally initialized by RESET input. The reset input must be held for at least 1 ms. Instruction Set Initialization: 1. Start oscillation executed 2. Driver output control (SGS = 0, CMS = 0) 3. Power control (AMP = 0: LCD power off, SLP = 0: Sleep mode off, STB = 0: Standby mode off) 4 ...
Page 37
... ID pin. The five upper bits must be 01110. Two different chip addresses must be assigned to a single HD66740 because the seventh bit of the start byte is used as a register select bit (RS): that is, when instruction can be issued, and when data can be written to or read from RAM ...
Page 38
... SDA Start byte Dummy read 1 (Input R output) Start Note: Two bytes of the RAM read data after the start byte are invalid. The HD66740 starts to read the correct RAM data from the third byte. Figure 16 Clock-synchronized Serial Interface Timing Sequence ...
Page 39
... HD66740W instruction or as RAM data. Having received 8-bit data normally, HD66740W pulls down the ninth bit (ACK low level. The instruction or RAM data is 8-bits data format. Two bytes of RAM read data after the start byte are invalid. The HD66740W start to read correct RAM data from third byte. ...
Page 40
... HD66740 a) Basic data-receive timing through the I2C bus interface Transfer start SCL (input) SDA "0" "1" "1" "1" "0" "0" (input/ output) Device ID code RS RW Start byte Acknowledge b) Consecutive data-receive timing through the I2C bus interface ...
Page 41
... Note: Transfer synchronization function for a 4-bit bus interface The HD66740 supports the transfer synchronization function which resets the upper/lower counter to count upper/lower 4-bit data transfer in the 4-bit bus interface. Noise causing transfer mismatch between the four upper and lower bits can be corrected by a reset triggered by consecutively writing a 0000 instruction four times ...
Page 42
... HD66740 Oscillation Circuit The HD66740 can either be supplied with operating pulses externally (external clock mode) or oscillate using an internal R-C oscillator with an external oscillator-resistor (external resistor oscillation mode). Note that in R-C oscillation, the oscillation frequency is changed according to the internal capacitance value, the external resistance value, or operating power-supply voltage. ...
Page 43
... V1 V2 COM1 V5 GND V1 V2 COM2 V5 GND V1 V2 COM79 V5 GND V1 V2 COM80 V5 GND 1 frame Figure 20 LCD Drive Output Waveform (B-pattern AC Drive with 1/80 Multiplexing Duty frame Ratio) 43 HD66740 79 80 ...
Page 44
... HD66740 n-raster-row Reversed AC Drive The HD66740 supports not only the LCD reversed AC drive in a one-frame unit (B-pattern waveform) but also the n-raster-row reversed AC drive which alternates in an n-raster-row unit from one to 32 raster-rows (C-pattern waveform). When a problem affecting display quality occurs, such as crosstalk at high-duty driving of more than five lines (1/40 duty), the n-raster-row reversed AC drive (C-pattern waveform) can improve the quality ...
Page 45
... Here, contrast can be adjusted by software through the CT bits of the contrast adjustment register. The HD66740 incorporates a voltage-follower operational amplifier for each reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. Thus, potential differences between V higher. Note that the OPOFF pin must be grounded when using the operational amplifiers. Place a capacitor of about 0.1 µ ...
Page 46
... In this case, Vci must be equal to or smaller than the V The HD66740 incorporates a voltage-follower operational amplifier for each reduce current flowing through the internal bleeder-resistors, which generate different liquid-crystal drive voltages ...
Page 47
... Internal Booster for LCD Drive Voltage Generation Thermistor Figure 24 OPOFF = GND HD66740 V LCD V1OUT - V2OUT LCD R driver V3OUT V4OUT V5OUT R GND GND Vci C1+ C1- C2+ Booster C2- C3+ C3- C3+ C3- HD66740 Vcc Vcc Vci Tr GND Temperature Compensation Circuit 47 HD66740 SEG1 to SEG112 COM1 to COM80 ...
Page 48
... HD66740 Notes on Using Internal Operational Amplifier The HD66740 has a low-current-consumption-type operational amplifier. When a low-voltage supply is used, particularly at low temperatures near –20 C, the current in the operational amplifier is reduced. Therefore, depending on the specifications or display pattern of the LCD panel used, screen quality may be poor or the LCD panel may not operate at all. ...
Page 49
... Countermeasures for Screen Quality when Using On-chip Operational Amplifier The HD66740 is an on-chip LCD driver that has an LCD power supply for high duty. Screen quality is affected by the load current of the high-duty LCD panel used. When the bias (1/10 bias, 1/9.5 bias, 1/9 bias, etc.) is high and the displayed pattern is completely or almost completely white, the white sections may appear dark ...
Page 50
... HD66740 Switching the Boosting Multiplying Factor Instruction bits (BT1/0 bits) can optionally select the boosting multiplying factor of the internal booster. According to the display status, power consumption can be reduced by changing the LCD drive duty and the LCD drive bias, and by controlling the boosting multiplying factor for the minimum requirements. ...
Page 51
... Example of Power-supply Voltage Generator for More Than Five-times Boosting Output The HD66740 incorporates the booster for up to five-times boosting. However, the LCD drive voltage (VLCD) will not be enough for five-times boosting from Vcc when the power-supply voltage of Vcc is low or when the LCD drive voltage is high for the high-contrast LCD display. In this case, the reference voltage (Vci) for boosting can be set higher than the power-supply voltage of Vcc ...
Page 52
... R unit within a range from 0. through 3. where reference resistance obtained by dividing the total resistance. The HD66740 incorporates a voltage-follower operational amplifier for each reduce current flowing through the internal bleeder resistors, which generate different liquid-crystal drive voltages. Thus, CT5-0 bits must be adjusted so that the potential differences between V between V5 and GND are 0 ...
Page 53
... Potential Difference Display Color between V1 and GND 3. (Small 1.15x (Large) 0. HD66740 (Light) (Deep) ...
Page 54
... HD66740 Table 20 Contrast Adjustment per Bias Drive Voltage Bias LCD drive voltage LCD drive voltage adjustment range 1/ Limit of potential GND) bias LCD difference between V5 and GND drive - Limit if potential difference between VLCD and V1 - LCD drive voltage adjustment range 1/9 ...
Page 55
... Table 21 LCD drive duty ratio 1/80 1/72 (NL3-0 set value) 1001 1000 Optimum drive bias 1/10 1/9.5 value (BS2-0 set value) 000 001 Optimum Drive Bias Values 1/64 1/56 1/48 1/40 1/32 0111 0110 0101 0100 0011 1/9 1/8 1/8 1/7 1/6 010 011 011 100 101 55 HD66740 1 1/24 1/16 1/8 0010 0001 0000 1/6 1/5 1/4 101 110 111 ...
Page 56
... HD66740 VLCD VLCD 5. GND GND GND GND bias ii) 1/ 9.5 bias (BS2–0 = 000) (BS2–0 = 001) VLCD VLCD GND ...
Page 57
... LCD Panel Interface The HD66740 has a function for changing the common driver/segment driver output shift direction using the CMS bit and SGS bit to meet the chip mounting positions of the HD66740. interface wiring to the LCD panel with COG or TCP installed. HITACHI Ltd. ...
Page 58
... HD66740 SEG112/1 COM72/9 COM41/40 COM8/73 COM1/80 Figure 30 Table 22 Number of Left and Right Extension Lines of Common Driver Drive Duty Ratio Left Edge of Screen 1/48 16 (COM1–8, 41–48) 1/56 24 (COM1–8, 41–56) 1/64 32 (COM1–8, 41–64) 1/72 40 (COM1–8, 41–72) 1/80 40 (COM1–8, 41–72) LCD PANEL SEG1/112 COM80/1 ...
Page 59
... Figure 31 Display Example in Graphics Display Mode Vertical Smooth Scroll Display The HD66740 can scroll character and graphics display vertically in units of raster-rows. This is achieved by writing display data into a one-line area that is not being used for display. In other words, 59 HD66740 ...
Page 60
... HD66740 one line can be used to achieve continuous smooth vertical scroll even in a 9-line or less display. Here, after the 10th line is displayed, the first line is displayed again. When the 10th line is fully displayed, all one-line display data must be rewritten immediately after scrolling because there is no non-displayed area ...
Page 61
... Scroll up 20 raster-rows (5th raster-row of 3rd line displayed at the top) 1 SN3–SN0 = 0011 SL2–SL0 = 000 (1st raster-row of 4th line displayed at the top) Scroll up 28 raster-rows (5th raster-row of 4th line displayed at the top) 61 HD66740 ...
Page 62
... HD66740 Partial Smooth Scroll Display Function The HD66740 can partially fixed-display the areas of a graphics icon, such as a pictogram or a menu bar, and perform vertical smooth scrolling of the remaining bit-map areas. Since the PS1 to PS0 bits do not perform smooth scrolling of the upper first to third display lines but does fixed-display, pictograms can be placed ...
Page 63
... They do not depend on the setting values of the 63 HD66740 SN3–0 SN3–0 = 0011 = 0100 6th line 4th line 5th line 7th line 5th line 6th line ...
Page 64
... HD66740 Partial Smooth Scroll Display Examples Table 24 Data Setting to the CGRAM Partial Smooth Scroll Display Examples CGRAM Address "000" to "06F" "080" to "0EF" "100" to "16F" "180" to "1EF" "200" to "26F" "280" to "2EF" "300" to "36F" "380" to "3EF" "400" to "46F" "480" to "4EF" i) Initial screen display - PS1-0 = " ...
Page 65
... Fixed display (1st line) Figure 34 Example of Display Screen in the Partial Smooth Scroll Mode (1) Fixed display (2nd line) Fixed display (1st line) Figure 35 Example of Display Screen in the Partial Smooth Scroll Mode (2) Display start setting position Display start setting position 65 HD66740 ...
Page 66
... HD66740 Double-height Display The HD66740 can double the height of any desired line from the first to 10th lines. A line can be selected by the DL1 to DL10 bits as listed in table 25. All graphics display patterns stored in the CGRAM can be doubled in height, allowing easy recognition. Note that there should be no space between the lines for double-height display (figure 36) ...
Page 67
... Reversed Display Function The HD66740 can display character/graphics display sections by black-and-white reversal. Black- and-white reversal can be easily displayed when REV is set to 1. Figure 37 REV = 1 (Reversed display) Reversed Display 67 HD66740 ...
Page 68
... For example, in the 10-line display mode (1/80 duty ratio), the HD66740 can selectively drive only the center of the screen or only the top or bottom of the screen by combining these register functions and the centering display (CN1– ...
Page 69
... Figure 38 Partial-on Display (Date and Time Indicated) (1) - 1/32 duty drive at the center of the screen Figure 39 Partial-on Display (Date and Time Indicated) (2) Always applying non-selection level Always applying selection level 69 HD66740 ...
Page 70
... HD66740 Sleep Mode Setting the sleep mode bit (SLP puts the HD66740 in the sleep mode, where the device stops all internal display operations, thus reducing current consumption. Specifically, LCD drive is completely halted. Here, all the SEG (SEG1 to SEG112) and COM (COM1 to COM80) pins output the GND level, resulting in no display ...
Page 71
... Standby Mode Setting the standby mode bit (STB puts the HD66740 in the standby mode, where the device stops completely, halting all internal operations including the R-C oscillation circuit, thus further reducing current consumption compared to that in the sleep mode. Specifically, character and segment displays, which are controlled by the multiplexing drive method, are completely halted ...
Page 72
... HD66740 Absolute Maximum Ratings Item Symbol Power supply voltage ( Power supply voltage (2) V – GND LCD Input voltage Vt Operating temperature Topr Storage temperature Tstg Notes the LSI is used above these absolute maximum ratings, it may become permanently damaged. Using the LSI within the following electrical characteristics limits is strongly recommended for normal operation ...
Page 73
... R-C oscillation ° kHz (1/72 duty) 0.1 5 µ 25° µ LCD °C, f 1/9 bias, VTEST3=“High” — 15 HD66740 Notes OSC 7, 8 OSC kHz, OSC 9 ...
Page 74
... HD66740 Booster Characteristics Item Symbol Min Triple-boost V 8.5 UP3 output voltage (VLOUT pin) Quadruple- V 11.5 UP4 boost output voltage (VLOUT pin) Five-times- V 14.5 UP5 boost output voltage (VLOUT pin) Use range UP3 CC boost output V , UP4 voltage V UP5 Note: For the numbered notes, refer to the Electrical Characteristics Notes section following these tables ...
Page 75
... AHE t 60 — — DSWE t 20 — — — — 300 DDRE t 5 — — DHRE 75 HD66740 Notes Test Condition ns Figure 47 ns Figure 47 ns Figure 47 ns Figure 47 ns Figure 47 ns Figure 47 ns Figure 47 ns ...
Page 76
... HD66740 (Vcc = 2.7 to 3.6 V) Item Enable cycle time Write Read Enable high-level pulse width Write Read Enable low-level pulse width Write Read Enable rise/fall time Setup time (RS, R CS*) Address hold time Write data setup time Write data hold time Read data delay time ...
Page 77
... DSW t 20 — — — — 200 ns DDR t 5 — — ns DHR 77 HD66740 Test Condition Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Test Condition Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 Figure 48 ...
Page 78
... HD66740 Clock-synchronized Serial Interface Timing Characteristics ( 1 Item Serial clock cycle time At write (receive) At read (send) Serial clock high-level width At write (receive) At read (send) Serial clock low-level width At write (receive) At read (send) Serial clock rise/fall time Chip select setup time ...
Page 79
... SIH t — — 200 SOD t 5 — — SOH = 1.8 to 3.6 V) Min Typ Max 1 — — 79 HD66740 Unit Test Condition µs Figure 49 µs Figure 49 ns Figure 49 ns Figure 49 ns Figure 49 ns Figure 49 ns Figure 49 ns Figure 49 ns Figure 49 ns Figure 49 ...
Page 80
... HD66740 I2C Bus Interface Timing Characteristics (Vcc = 1.8 to 3.6 V) Item SCL clock frequency SCL clock high-level pulse width SCL clock low-level pulse width SCL/SDA rise time SCL/SDA fall time Bus free time Start condition hold time Setup time for a repeated START condition ...
Page 81
... PMOS NMOS GND Vcc PMOS (Input circuit) NMOS Vcc (Tri-state output circuit) PMOS NMOS GND Vcc PMOS (Input circuit) NMOS Vcc (Tri-state output circuit) PMOS NMOS GND I/O Pin Configuration 81 HD66740 Output enable Output data IM1 IM2 Output enable Output data IM1 ...
Page 82
... HD66740 3. The TEST pin must be grounded and the IM2/1, IM0/ID, and OPOFF pins must be grounded or connected to Vcc. 4. Corresponds to the high output for clock-synchronized serial interface. 5. Applies to the resistor value (RCOM) between power supply pins V1OUT, V2OUT, V5OUT, GND and common signal pins, and resistor value (RSEG) between power supply pins V1OUT, V3OUT, V4OUT, GND and segment signal pins, when current Id is flown through all driver output pins ...
Page 83
... Vcc Vci VLOUT GND 1 F Figure 45 Booster 83 HD66740 Vcc = 3.6 V 121 kHz 92 kHz 83 kHz 77 kHz 71 kHz 66 kHz 60 kHz 54 kHz + C1 C1 C2 C3- + C4+ ...
Page 84
... HD66740 Referential data VUP4 = VLCD – GND; VUP5 = VLCD – GND (i) Relation between the obtained voltage and input voltage Quadruple boosting 16.0 12.0 VUP4 (V) 8.0 4.0 1.0 2.0 3.0 Vci (V) Vci = Vcc, fosc = 86 kHz DCC = 0 (ii) Relation between the obtained voltage and temperature Quadruple boosting 14.0 12.0 10.0 VUP4 (V) 8.0 -60 ...
Page 85
... Vci = Vcc = 3.0 V, fosc = 86 kHz DCC = 0 Figure 45 Load Circuits AC Characteristics Test Load Circuits Data bus: DB7 to DB0, SDA Test Point Five-times boosting 15.5 typ. 15.0 VUP5 (V) 14.5 14.0 13.5 150 200 0 50 Vci = Vcc = 3.0 V, fosc = 86 kHz DCC = 0 Booster (cont Figure 46 Load Circuit 85 HD66740 typ. 100 150 200 ...
Page 86
... HD66740 Timing Characteristics 68-system Bus Operation R ASE CS DB0 to DB7 DB0 to DB7 Note specified in the overlapped period when CS* is low high. EH Figure AHE CYCE ...
Page 87
... LW WRf t t CYCW, CYCR t t DSW HWR Write data DDR DHR V V OH1 OH1 Read data V V OL1 OL1 80-system Bus Timing 87 HD66740 ...
Page 88
... HD66740 Clock-synchronized Serial Operation Start CSU V IH SCL V IL SDA t SOD SDA Figure 49 Clock-synchronized Serial Interface Timing Reset Operation RESET SCYC tscf tscr t t CWL SCH SISU SIH Input data ...
Page 89
... VIH VIH VIH SD A VIL2 VIL2 SCL SCLH SCL VIH VIL2 SCLL S r Figure 51 Re peat ed Start : Sr VIH VIH VIL2 DAH SDAS t STAS VIH VIH I2C bus Interface Timing 89 HD66740 S top : P VIL2 STOS ...
Page 90
... HD66740 Power-on/off Sequence To prevent pulse lighting of LCD screens at power-on/off, the power-on/off sequence is activated as shown below. However, since the sequence depends on LCD materials to be used, confirm the conditions by using your own system. Power-on Sequence Turn on power voltages Vcc and Vci, RESET = "Low" ...
Page 91
... Vcc Power voltage: Vcc GND Vcc RESET GND Oscillation state Oscillation stabilization time Vcc Signal-input instruction issued GND Note: CR oscillation starts by power-on and input reset. The standby mode is cleared by input reset. Figure 53 Power-on reset time Power-on Timing 91 HD66740 ...
Page 92
... HD66740 Power-off Sequence Issue LCD power instruction Turn off power voltages Vcc and Vci To the power-on sequence Figure 54 Vcc Power voltage: Vcc GND Vcc RESET GND V1OUT Driver SEG/ COM output GND Note: When hardware reset is input during the power-off period, the D bit is cleared to 0 and SEG/COM output is forcibly lowered to the GND level ...
Page 93
... Remove character and super-imposed display related explanations. - Revision 0.6 (January. 2001) Support 1.8V low voltage operation. - Corrected corner PAD number (p6). - Added VTEST usage (p48) and operational amplifier usage (p49). - Changed R-C Oscillation Frequency of Table 28 (p83). - Added I2C interface (HCD66740WBP, HD66740WTB0). - Revision 0.7 (January. 2001) Added power on/off sequence. - HD66740 ...
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... HD66740 When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All right reserved: No one is permitted to reproduce or duplicated, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document ...
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