mx25l12845e Macronix International Co., mx25l12845e Datasheet - Page 29

• Manufacturer Part Number: mx25l12845e
• Description: Mx25l12845e High Performance Serial Flash Specification Preliminary
• Manufacturer: Macronix International Co.

P/N: PM1428
Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP
mode, "0" indicates not in CP mode; "1" indicates in CP mode.
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This bit will also
be set when the user attempts to program a protected main memory region or a locked OTP region. This bit can in-
dicate whether one or more of program operations fail, and can be reset by command CLSR (30h)
Erase Fail Flag bit. While a erase failure happened, the Erase Fail Flag bit would be set. This bit will also be set
when the user attempts to erase a protected main memory region or a locked OTP region. This bit can indicate
whether one or more of erase operations fail, and can be reset by command CLSR (30h)
Write Protection Select bit. The Write Protection Select bit indicates that WPSEL has been executed successfully.
Once this bit has been set (WPSEL=1), all the blocks or sectors will be write-protected after the power-on every
time. Once WPSEL has been set, it cannot be changed again, which means it's only for individual WP mode.
Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once
WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
Security Register Definition
(27) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values
of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Se-
cured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
1=individual
non-volatile
(default=0)
WP mode
WP mode
0=normal
WPSEL
bit7
bit
Erase failed
(default=0)
1=indicate
volatile bit
0=normal
succeed
E_FAIL
Erase
bit6
(default=0)
1=indicate
volatile bit
0=normal
Program
Program
succeed
P_FAIL
failed
bit5
Continuously
1=CP mode
(CP mode)
(default=0)
volatile bit
0=normal
Program
Program
mode
mode
bit4
29
volatile bit
reserved
bit3
x
volatile bit
reserved
MX25L12845E
bit2
x
non-volatile
(indicate if
lock-down
lockdown
program/
1 = lock-
(cannot
0 = not
LDSO
erase
down
OTP)
bit1
bit
REV. 0.06, MAR. 05, 2009
indicator bit
non-volatile
nonfactory
1 = factory
Secrured
OTP
lock
lock
bit0
0 =
bit