mx25l6405 Macronix International Co., mx25l6405 Datasheet - Page 15

• Manufacturer Part Number: mx25l6405
• Description: Tm 64m-bit [x 1] Cmos Serial Eliteflash Memory
• Manufacturer: Macronix International Co.

MX25L6405
(9) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector
(see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary
(the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS#
goes high. (see Figure 20)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and
sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by
BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
(10) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must
execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table
3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth
of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low-> sending CE instruction code-> CS# goes high. (see Figure
21)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tBE timing, and
sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3,
BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1,
BP0 all set to "0".
(11) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must
execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least significant
address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed
from the start address if the same page (from the address whose 8 least significant address bits (A7-A0) are all 0). The
CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the byte boundary( the latest
eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. If more than 256 bytes
are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be
disregarded. If less than 256 bytes are sent to the device, the data is programmed at the request address of the page
without effect on other address of the same page.
The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at least
1-byte on data on SI-> CS# goes high. (see Figure 19)
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and
sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected
by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
P/N: PM1107
REV.1.3, NOV. 06, 2006
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