SI3200-X-FS SILABS [Silicon Laboratories], SI3200-X-FS Datasheet - Page 16
SI3200-X-FS
Manufacturer Part Number
SI3200-X-FS
Description
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
1.SI3200-X-FS.pdf
(112 pages)
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Si3220/25
Table 12. Switching Characteristics—SPI
V
16
Parameter
Cycle Time SCLK
Rise Time, SCLK
Fall Time, SCLK
Delay Time, SCLK Fall to SDO Active
Delay Time, SCLK Fall to SDO
Transition
Delay Time, CS Rise to SDO Tri-state
Setup Time, CS to SCLK Fall
Hold Time, CS to SCLK Rise
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time between Chip Selects
SDI to SDITHRU Propagation Delay
Note: All timing is referenced to the 50% level of the waveform. Input test levels are V
DDA
= V
DDA
SDITHRU
= 3.13 to 5.25 V, T
SCLK
SDO
SDI
CS
A
= 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade, C
t
su1
t
d1
Figure 1. SPI Timing Diagram
t
r
Symbol
t
t
t
t
t
t
t
t
t
su1
su2
t
d1
d2
d3
h1
h2
d4
t
t
cs
c
r
f
Rev. 1.2
Test Conditions
t
su2
t
c
t
d2
t
h2
t
d4
IH
Min
220
62
—
—
—
—
—
25
20
25
20
—
= V
L
DDD
t
= 20 pF
f
t
h1
–0.4 V, V
Typ
—
—
—
—
—
—
—
—
—
—
—
4
t
cs
IL
t
d3
= 0.4 V
Max
25
25
20
20
20
10
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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