SI3201-X-FS SILABS [Silicon Laboratories], SI3201-X-FS Datasheet
SI3201-X-FS
Related parts for SI3201-X-FS
SI3201-X-FS Summary of contents
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... V (Si3233M only supply. The ProSLIC controls the phone line through Silicon Labs’ Si3201 Linefeed IC or discrete circuitry. Si3233 features include software-configurable 5 REN internal ringing DTMF generation, and a comprehensive set of telephony signaling capabilities for operation with only one hardware solution ...
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Si3233 2 Preliminary Rev. 0.5 ...
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... Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4. Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 4.1. Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.2. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.3. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.4. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 5. Pin Descriptions: Si3233 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8. Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Preliminary Rev. 0.5 ...
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... Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad Symbol Si3233 DDD DDA1 DDA2 IND STG θ JA θ Si3201 BAT V INHV STG 3 θ Preliminary Rev. 0.5 Value Unit –0.5 to 6.0 V ±10 mA – ...
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... Parameter Ambient Temperature Ambient Temperature Si3233 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 Product specifications are only guaranteed when the typical application circuit (including component tolerances) is used ...
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Si3233 Table 3. AC Characteristics (Continued 3. 70°C for F-Grade, –40 to 85°C for G-Grade) DDA DDD A Parameter Longitudinal Impedance Longitudinal Current per Pin Notes: 1. Analog signal ...
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Table 4. Linefeed Characteristics ( 3. 70°C for F-Grade, –40 to 85°C for G-Grade) DDA DDD A Parameter Symbol Loop Resistance Range R LOOP DC Loop Current Accuracy DC Open ...
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Si3233 Table 5. Monitor ADC Characteristics ( 3. 70°C for F-Grade, –40 to 85°C for G-Grade) DDA DDD A Parameter Symbol Differential Nonlinearity DNLE (6-bit resolution) Integral Nonlinearity INLE (6-bit ...
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... Table 8. Power Supply Characteristics ( 3. 5. 70°C for F-Grade, –40 to 85°C for G-Grade) DDA DDD A Parameter Symbol Power Supply Current Analog and Digital V Supply Current (Si3201 Supply Current BAT Notes 3.3 V. DDD DDA 5.25 V. ...
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Si3233 Table 9. Switching Characteristics—General Inputs 3. 70°C for F-Grade, –40 to 85°C for G-Grade, C DDA DDA A Parameter Rise Time, RESET RESET Pulse Width Note: All timing ...
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SCLK t su1 CS SDI t d1 SDO Figure 2. SPI Timing Diagram t thru su2 Preliminary Rev. 0.5 Si3233 ...
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... All circuit ground should have a single- 15 point connection to the ground plane. 4. Si3201 bottom-side exposed should be electronically and thermally connected to talk ground plane. Figure 3. Si3233/Si3233M Application Circuit Using Si3201 Table 11. Si3233/Si3233M + Si3201 External Component Values Component(s) C1,C2 10 µ Ceramic Low Leakage Electrolytic, ±20% C3,C4 C5,C6 C15,C16,C17,C24 ...
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SDCH SDCL DCFF DCDRV Notes: 1. Values and configurations for these components can be derived from Table 17 or from App Note 45. 2. Voltage rating for C14 and C25 must be greater than VDC. Figure 4. Si3233 DC-DC Converter ...
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Si3233 SDCH SDCL DCFF DCDRV Figure 5. Si3233M MOSFET/Transformer DC-DC Converter Circuit Table 13. Si3233M MOSFET/Transformer DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20%, low ESR (tan(δ) < 0.08) C14* C25* 10 µF, Electrolytic, ±20%, low ...
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Q1 5401 R10 10 TIP Q6 5551 C8 C5 220nF 22nF R6 C6 80.6 22nF RING Notes: 1. Values and configurations for these components can be derived from Table 16 or from App Note 45. 2. Only one component per ...
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Si3233 Table 14. Si3233/Si3233M External Component Values—Discrete Solution (Continued) R15 R21 1/10 W, ±1% (See AN45 or Table 16 for value selection) R28,R29 R32* *Note: Only one component per system needed. VINp TX gain = 0.6622 CMlevel VINm VOUTm VOUTp ...
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Table 16. Component Value Selection for Si3233 Component R28 1/ resistor For V DD For V DD R29 1/ resistor For V CLAMP For V CLAMP For V CLAMP Table 17. Component Value Selection Examples for ...
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... DTMF tones, phase continuous FSK (caller ID) signaling, and call progress tones. The Si3201 linefeed interface IC performs all high voltage functions. The Si3201 can also be replaced with low-cost discrete circuits as shown in the typical application in Figure 6. The Si3233 is designed to be used with Broadcom ...
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... A “direct” register is one that is mapped directly. 2.2.2. Linefeed Architecture The Si3233 uses either the Si3201 linefeed interface low-cost external circuit to generate the high voltages required for subscriber line interfaces. The ProSLIC uses both voltage and current sensing to control TIP and RING ...
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Si3233 Table 20. ProSLIC Linefeed Operations LF[2:0]* Linefeed State 000 Open 001 Forward Active 010 Forward On-Hook Transmission 011 TIP Open 100 Ringing 101 Reverse Active 110 Reverse On-Hook Transmission 111 Ring Open Note: The Linefeed register (LF) is located ...
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Power Monitoring and Line Fault Detection In addition to reporting voltages and currents, the ProSLIC continuously monitors the power dissipated in each linefeed transistor. Realtime output power of any one of the six linefeed transistors can be read by ...
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Si3233 Table 22. Associated Power Monitoring and Power Fault Registers (Continued) Power Alarm Interrupt Enable Power Alarm Automatic/Manual Detect *Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. ...
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Voltage-Based Loop Closure Detection An optional voltage-based loop closure detection mode is enabled by setting LCVE = 1 (direct Register 108, bit 2). In this mode, the loop voltage is compared to the loop closure threshold register represents a ...
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Si3233 solution from a single 3 power supply. By nature of a dc-dc converter’s operation, peak and average input currents can become large with small input voltages. Consider this when selecting the appropriate input voltage and ...
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TRACK = 1 mode. Therefore, the brief on-hook voltage measurement would yield approximately the same voltage ...
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Si3233 2.3.6. DC-DC Converter During Ringing When the ProSLIC enters the ringing state, it requires voltages well above those used in the active mode. The voltage to be generated and regulated by the dc-dc converter during a ringing burst is ...
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Oscillator Frequency and Amplitude Each of the two tone generators contains a two-pole resonant oscillator circuit with frequency and amplitude, which are programmed via indirect registers OSC1, OSC1X, OSC1Y, OSC2, OSC2X, and OSC2Y. The sample rate for the two ...
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Si3233 Table 25. Associated Tone Generator Registers Parameter Oscillator 1 Frequency Coefficient Oscillator 1 Amplitude Coefficient Oscillator 1 initial phase coefficient Oscillator 1 Active Timer Oscillator 1 Inactive Timer Oscillator 1 Control Parameter Oscillator 2 Frequency Coefficient Oscillator 2 Amplitude ...
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Enhanced FSK Waveform Generation Enhanced FSK generation can be enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6). In this mode, the user can define mark (1) and ...
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Si3233 Table 26. Registers for Ringing Generation (Continued) Ringing amplitude Ringing initial phase Common Mode Bias Adjust During Ringing Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. ...
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T 1 ---------- - t = – ⎝ RISE 4 CF where T = ringing period, and CF = desired crest factor. For example, to generate signal, the equations are as follows: ...
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Si3233 Linefeed Shadow register (direct Register 64). The data then feeds into a programmable digital low pass filter, which removes unwanted ac signal components before threshold detection. The output of the low pass filter is compared to a programmable threshold, ...
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Table 28. Recommended Ring Trip Values for Ringing Ringing NRTP Frequency Hz decimal 16.667 64 20 100 30 112 40 128 50 213 60 256 RPTP hex decimal hex 0200 34 mA 3600 0320 34 mA 3600 0380 34 mA ...
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Si3233 2.6. Two-Wire Impedance Matching The ProSLIC provides on-chip programmable two-wire impedance settings to meet a wide variety of worldwide two-wire return loss requirements. The two-wire impedance is programmed by loading one of the eight available impedance values into the ...
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The interrupt control block will then set the associated bit in the interrupt status register if the enable bit for that interrupt is set. The INT pin is a NOR of the ...
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Si3233 SCLK CS SDI SDO SCLK CS SDI SDO High Impedance 36 Don't Care High Impedance Figure 16. Serial Write 8-Bit Mode Don't Care ...
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SDO CPU CS SDI Chip Select Byte SCLK SDI0 SDI1 – SDI2 – – SDI3 – – – C7 ...
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Si3233 3. Control Registers Indirect registers are accessed through direct registers 28 through 31. Instructions on how to access them is described in “4. Indirect Registers” beginning on page 85. Note: Any register not listed here is reserved and must ...
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Table 29. Direct Register Summary (Continued) Register Name 38 Oscillator 1 Inactive Timer—Low Byte 39 Oscillator 1 Inactive Timer—High Byte 40 Oscillator 2 Active Timer—Low Byte 41 Oscillator 2 Active Timer—High Byte 42 Oscillator 2 Inactive Timer—Low Byte 43 Oscillator ...
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Si3233 Table 29. Direct Register Summary (Continued) Register Name 75 Low Battery Voltage 76 Power Monitor Pointer 77 Line Power Output Monitor 78 Loop Voltage Sense 79 Loop Current Sense 80 TIP Voltage Sense 81 RING Voltage Sense 82 Battery ...
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Table 29. Direct Register Summary (Continued) Register Name 101 Common Mode Loop Current Gain Calibration Result 102 Current Limit Calibration Result 103 Monitor ADC Offset Calibration Result 104 Analog DAC/ADC Offset 105 DAC Offset Calibration Result 106 Common Mode Balance ...
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Si3233 Register 0. SPI Mode Select Bit D7 D6 Name SPIDC SPIM Type R/W R/W Reset settings = 00xx_xxxx Bit Name 7 SPIDC SPI Daisy Chain Mode Enable Disable SPI daisy chain mode Enable SPI daisy ...
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Register 9. Audio Gain Control Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 ARX[1:0] Analog Receive Path Gain –3 3 ...
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Si3233 Register 10. Two-Wire Impedance Synthesis Control Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation Off ...
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Register 14. Power Down Control 1 Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4 DCOF DC-DC Converter Power-Off Control Automatic power control Override automatic control and force ...
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Si3233 Register 15. Power Down Control 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3 DACM Digital to Analog Converter Manual/Automatic Power Control Automatic power control Manual ...
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Register 18. Interrupt Status 1 Bit D7 D6 Name RGIP Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 RGIP Ringing Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt ...
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Si3233 Register 19. Interrupt Status 2 Bit D7 D6 Name Q6AP Q5AP Q4AP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt ...
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Register 20. Interrupt Status 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1 INDP Indirect Register Access Serviced Interrupt. This bit is set once a pending indirect register service request has ...
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Si3233 Register 21. Interrupt Enable 1 Bit D7 D6 Name RGIE Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 RGIE Ringing Inactive Timer Interrupt Enable Interrupt masked Interrupt enabled. 4 RGAE ...
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Register 22. Interrupt Enable 2 Bit D7 D6 Name Q6AE Q5AE Q4AE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AE Power Alarm Q6 Interrupt Enable Interrupt masked Interrupt enabled. 6 Q5AE Power Alarm ...
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Si3233 Register 23. Interrupt Enable 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1 INDE Indirect Register Access Serviced Interrupt Enable Interrupt masked Interrupt enabled. 0 Reserved ...
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Register 28. Indirect Data Access—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 IDA[7:0] Indirect Data Access—Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA into ...
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Si3233 Register 30. Indirect Address Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IAA[7:0] Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect ...
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Register 32. Oscillator 1 Control Bit D7 D6 Name OSS1 REL Type R R/W Reset settings = 0000_0000 Bit Name 7 OSS1 Oscillator 1 Signal Status Output signal inactive Output signal active. 6 REL Oscillator 1 ...
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Si3233 Register 33. Oscillator 2 Control Bit D7 D6 Name OSS2 Type R Reset settings = 0000_0000 Bit Name 7 OSS2 Oscillator 2 Signal Status Output signal inactive Output signal active. 6 Reserved Read returns zero. ...
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Register 34. Ringing Oscillator Control Bit D7 D6 Name RSS RDAC Type R Reset settings = 0000_0000 Bit Name 7 RSS Ringing Signal Status Ringing oscillator output signal inactive Ringing oscillator output signal active. 6 Reserved ...
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Si3233 Register 36. Oscillator 1 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[7:0] Oscillator 1 Active Timer. LSB = 125 µs Register 37. Oscillator 1 Active Timer—High Byte Bit D7 D6 Name ...
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Register 39. Oscillator 1 Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT1[15:8] Oscillator 1 Inactive Timer. Register 40. Oscillator 2 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 ...
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Si3233 Register 42. Oscillator 2 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[7:0] Oscillator 2 Inactive Timer. LSB = 125 µs Register 43. Oscillator 2 Inactive Timer—High Byte Bit D7 D6 Name ...
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Register 49. Ringing Oscillator Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RAT[15:8] Ringing Active Timer. Register 50. Ringing Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit ...
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Si3233 Register 52. FSK Data Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. 0 FSKDAT FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register ...
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Register 64. Linefeed Control Bit D7 D6 Name LFS[2:0] Type Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual realtime linefeed state. Automatic operations may cause actual linefeed state ...
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Si3233 Register 65. External Bipolar Transistor Control Bit D7 D6 Name SQH Type R/W Reset settings = 0110_0001 Bit Name 7 Reserved Read returns zero. 6 SQH Audio Squelch squelch STIPAC and SRINGAC pins squelched. ...
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Register 66. Battery Feed Control Bit D7 D6 Name Type Reset settings = 0000_0011 Bit Name 7:5 Reserved Read returns zero. 4 VOV Overhead Voltage Range Increase. This bit selects the programmable range for ...
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Si3233 Register 67. Automatic/Manual Control Bit D7 D6 Name MNCM MNDIF Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 MNCM Common Mode Manual/Automatic Select Automatic control Manual control, in which ...
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Register 68. Loop Closure/Ring Trip Detect Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 DBIRAW Ring Trip/Loop Closure Unfiltered Output. State of this bit reflects the realtime output of ring ...
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Si3233 Register 70. Ring Trip Detect Debounce Interval Bit D7 D6 Name Type Reset settings = 0000_1010 Bit Name 7 Reserved Read returns zero. 6:0 RTDI[6:0] Ring Trip Detect Debounce Interval. The value written to this register defines the minimum ...
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Register 72. On-Hook Line Voltage Bit D7 D6 Name VSGN Type R/W Reset settings = 0010_0000 Bit Name 7 Reserved Read returns zero. 6 VSGN On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage polarity ...
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Si3233 Register 74. High Battery Voltage Bit D7 D6 Name Type Reset settings = 0011_0010 Bit Name 7:6 Reserved Read returns zero. 5:0 VBATH[5:0] High Battery Voltage. The value written to this register sets high battery voltage. VBATH must be ...
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Register 76. Power Monitor Pointer Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2:0 PWRMP[2:0] Power Monitor Pointer. Selects the external transistor from which to read power output. The power of the ...
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Si3233 Register 78. Loop Voltage Sense Bit D7 D6 Name LVSP Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 LVSP Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage ...
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Register 80. TIP Voltage Sense Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VTIP[7:0] TIP Voltage Sense. This register reports the realtime voltage at TIP with respect to ground. The range (0x00) to ...
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Si3233 Register 83. Battery Voltage Sense 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VBATS2[7:0] Battery Voltage Sense 2. This register is one of two registers that reports the realtime voltage ground. ...
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Register 86. Transistor 3 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ3[7:0] Transistor 3 Current Sense. This register reports the realtime current through Q3. The range (0x00) to 9.59 mA ...
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Si3233 Register 89. Transistor 6 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ6[7:0] Transistor 6 Current Sense. This register reports the realtime current through Q6. The range (0x00) to 80.58 ...
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Register 93. DC-DC Converter Switching Delay Bit D7 D6 Name DCCAL DCPOL Type R/W Reset settings = 0001_0100 (Si3233) Reset settings = 0011_0100 (Si3233M) Bit Name 7 DCCAL DC-DC Converter Peak Current Monitor Calibration Status. Writing a one to this ...
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Si3233 Register 96. Calibration Control/Status Register 1 Bit D7 D6 Name CAL CALSP Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 CAL Calibration Control/Status Bit. Setting this bit begins calibration of the entire system. ...
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Register 97. Calibration Control/Status Register 2 Bit D7 D6 Name Type Reset settings = 0001_1111 Bit Name 7:5 Reserved Read returns zero. 4 CALM1 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled or ...
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Si3233 Register 98. RING Gain Mismatch Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGMR[4:0] Gain Mismatch of IE Tracking Loop for RING Current. Register 99. TIP Gain Mismatch ...
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Register 101. Common Mode Loop Current Gain Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0001 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGC[4:0] Common Mode DAC Gain Calibration Result. Register 102. Current Limit Calibration Result Bit ...
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Si3233 Register 104. Analog DAC/ADC Offset Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3 DACP Positive Analog DAC Offset. 2 DACN Negative Analog DAC Offset. 1 ADCP Positive Analog ADC Offset. ...
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Register 107. DC Peak Current Monitor Calibration Result Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:4 Reserved Read returns zero. 3:0 CMDCPK[3:0] DC Peak Current Monitor Calibration Result. Register 108. Enhancement Enable Bit D7 D6 Name ...
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Si3233 Bit Name 2 LCVE Voltage-Based Loop Closure. Enables loop closure to be determined by the TIP-to-RING voltage rather than loop cur- rent Loop closure determined by loop current Loop closure determined by TIP-to-RING voltage. 1 ...
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Indirect Registers Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. ...
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Si3233 Table 31. Oscillator Indirect Registers Summary (Continued) Addr D15 D14 D13 D12 Table 32. Oscillator Indirect Registers Description Addr 0 Oscillator 1 Frequency Coefficient. Sets tone generator 1 frequency. 1 Oscillator 1 Amplitude Register. Sets tone ...
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Table 33. Digital Programmable Gain/Attenuation Indirect Registers Summary Addr D15 D14 D13 D12 D11 13 14 Table 34. Digital Programmable Gain/Attenuation Indirect Registers Description Addr. 13 Receive Path Digital to Analog Converter Gain/Attenuation. This register sets gain/attenuation for the receive ...
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Si3233 4.3. SLIC Control See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas ...
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Table 36. SLIC Control Indirect Registers Description (Continued) Addr 20 Power Alarm Threshold for Transistors Q3 and Q4. 21 Power Alarm Threshold for Transistors Q5 and Q6. 22 Loop Closure Filter Coefficient. 23 Ring Trip Filter Coefficient. 24 Thermal Low ...
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Si3233 Table 38. FSK Control Indirect Registers Description Addr 69 FSK Amplitude Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener- ating a space or “0”. When the ...
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Pin Descriptions: Si3233 Pin # Name 35 CS Chip Select. Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance. When active, the serial port is operational. 36 INT Interrupt. Maskable interrupt output. Open drain ...
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Si3233 Pin # Name 8 CAPP SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. 9 QGND Component Reference Ground. 10 CAPM SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback ...
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Pin # Name 28 TEST1 Test. Enables test modes for Silicon Labs internal testing. This pin should always be tied to ground for normal operation. 29 DCFF DC Feed-Forward/High Current General Purpose Output. Feed-forward drive of external bipolar transistors to ...
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... Si3233 6. Pin Descriptions: Si3201 Pin # Name Input/ Output 1 TIP I — 3 RING I/O 4 VBAT — 5 VBATH — 7 GND — 8 VDD — 10 SRINGE O 11 STIPE O 13 IRINGN I 14 IRINGP I 15 ITIPN I 16 ITIPP I Bottom-Side — Exposed Pad 94 TIP 1 16 ITIPP ITIPN ...
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... ProSLIC Si3233-X-GM ProSLIC Si3233M-X-FM ProSLIC Si3233M-X-GM ProSLIC Si3201-X-FS Line Interface Si3201-X-GS Line Interface Notes: 1. “X” denotes product revision. 2. Add an “R” at the end of the device to denote tape and reel options; 2500 quantity per reel. 3. All devices are lead-free and RoHS-compliant. ...
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Si3233 8. Package Outline: 38-Pin QFN Figure 19 illustrates the package details for the Si3233. Table 39 lists the values for the dimensions shown in the illustration. Figure 19. 38-Pin Quad Flat No-Lead Package (QFN) Table 39. Package Diagram Dimensions ...
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... Package Outline: 16-Pin SOIC Figure 20 illustrates the package details for the Si3201. Table 40 lists the values for the dimensions shown in the illustration . –A– Seating Plane Figure 20. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 40. Package Diagram Dimensions ...
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Si3233 OCUMENT HANGE IST Revision 0.1 to Revision 0.5 Updated Section "2.6. Two-Wire Impedance Matching" on page 34 and Register 10, “Two-Wire Impedance Synthesis Control,” on page 44. Removed invalid reference to ZEXT bit. 98 Preliminary Rev. ...
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N : OTES Preliminary Rev. 0.5 Si3233 99 ...
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Si3233 C I ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ProSLICinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all ...