SI3230 SILABS [Silicon Laboratories], SI3230 Datasheet - Page 97

• Manufacturer Part Number: SI3230
• Manufacturer: SILABS [Silicon Laboratories]

4.5. FSK Control
For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These
registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108,
bit 6) and REL = 1 (direct Register 32, bit 6).
Addr. D15
100
101
102
103
104
99
Addr.
31
32
33
34
35
36
37
38
39
40
41
42
43
D14
Common Mode Maximum Threshold for Speed-Up.
This register defines the positive common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
Power Alarm Threshold for Transistors Q1 and Q2.
Power Alarm Threshold for Transistors Q3 and Q4.
Power Alarm Threshold for Transistors Q5 and Q6.
Loop Closure Filter Coefficient.
Ring Trip Filter Coefficient.
Thermal Low Pass Filter Pole for Transistors Q1 and Q2.
Thermal Low Pass Filter Pole for Transistors Q3 and Q4.
Thermal Low Pass Filter Pole for Transistors Q5 and Q6.
Common Mode Bias Adjust During Ringing.
Recommended value of 0 decimal.
DC-DC Converter V
This register sets the overhead voltage, V
When the VOV bit = 0 (direct Register 66, bit 4), V
(VMIND = 0 to 6h). When the VOV bit = 1, V
(VMIND = 0 to 9h).
Reserved.
Loop Closure Threshold—Lower Bound.
This register defines the lower threshold for loop closure hysteresis, which is enabled in
bit 0 of direct Register 108. The range is 0–80 mA in 1.27 mA steps.
Table 38. SLIC Control Indirect Registers Description (Continued)
D13
Table 39. FSK Control Indirect Registers Summary
D12
D11
OV
Voltage (Si3230 only).
D10
Preliminary Rev. 0.96
D9
FSK0X[15:0]
FSK1X[15:0]
FSK01[15:0]
FSK10[15:0]
Description
FSK0[15:0]
FSK1[15:0]
D8
OV
, to be supplied by the dc-dc converter.
OV
D7
should be set between 0 and 13.5 V
OV
D6
should be set between 0 and 9 V
D5
D4
D3
D2
Si3230
D1
D0
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