SC9S12XS256J1MAA FREESCALE [Freescale Semiconductor, Inc], SC9S12XS256J1MAA Datasheet - Page 580
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SC9S12XS256J1MAA
Manufacturer Part Number
SC9S12XS256J1MAA
Description
HCS12 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.SC9S12XS256J1MAA.pdf
(736 pages)
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128 KByte Flash Module (S12XFTMR128K1V1)
19.3.2.13 Flash Reserved1 Register (FRSV1)
This Flash register is reserved for factory testing.
All bits in the FRSV1 register read 0 and are not writable.
19.3.2.14 Flash ECC Error Results Register (FECCR)
The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits
in the FECCRIX register (see
fault information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults the priority for fault recording is double bit fault over single bit fault.
All FECCR bits are readable but not writable.
580
Offset Module Base + 0x000D
Offset Module Base + 0x000E
Offset Module Base + 0x000F
Reset
Reset
Reset
W
W
W
R
R
R
0
0
0
0
7
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 19-21. Flash ECC Error Results Low Register (FECCRLO)
Figure 19-20. Flash ECC Error Results High Register (FECCRHI)
0
0
0
0
6
6
6
Figure 19-19. Flash Reserved1 Register (FRSV1)
Section
S12XS Family Reference Manual, Rev. 1.09
0
0
0
0
5
5
5
19.3.2.4). Once ECC fault information has been stored, no other
0
0
0
0
4
4
4
ECCR[15:8]
ECCR[7:0]
0
0
0
0
3
3
3
0
0
0
0
2
2
2
Freescale Semiconductor
0
0
0
0
1
1
1
0
0
0
0
0
0
0
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