sed1355 ETC-unknow, sed1355 Datasheet - Page 118
sed1355
Manufacturer Part Number
sed1355
Description
Sed1355 Embedded Ramdac Lcd/crt Controller
Manufacturer
ETC-unknow
Datasheet
1.SED1355.pdf
(509 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
sed1355F0A
Manufacturer:
EPSON/爱普生
Quantity:
20 000
Company:
Part Number:
sed1355FOA
Manufacturer:
EPSON
Quantity:
996
Part Number:
sed1355FOA
Manufacturer:
EPSON/爱普生
Quantity:
20 000
- Current page: 118 of 509
- Download datasheet (3Mb)
Page 112
bits 1-0
8.2.6 Power Save Configuration Registers
bit 7
bit 3
bits 2-1
SED1355
X23A-A-001-11
Power Save Configuration Register
REG[1Ah]
Power Save
Status
RO
n/a
Suspend Refresh Select Bits [1:0]
PCLK Divide Select Bits [1:0]
Note
PCLK Divide Select Bits [1:0]
These bits select the MCLK: PCLK frequency ratio
See section on “Maximum MCLK:PCLK Frequency Ratios” for selection of clock ratios.
Power Save Status
This is a read-only status bit.
This bit indicates the power-save state of the chip.
When this bit = 1, the panel has been powered down and the memory controller is either in self
refresh mode or is performing only
When this bit = 0, the chip is either powered up, in transition of powering up, or in transition of
powering down. See Section 15 Power Save Modes for details.
LCD Power Disable
This bit is used to override the panel on/off sequencing logic.
When this bit = 0 the LCDPWR output is controlled by the panel on/off sequencing logic.
When this bit = 1 the LCDPWR output is directly forced to the off state.
The LCDPWR “On/Off” polarity is configured by MD10 at the rising edge of RESET# (MD10 = 0
configures LCDPWR = 0 as the Off state; MD10 = 1 configures LCDPWR = 1 as the Off state).
Suspend Refresh Select Bits [1:0]
These bits specify the type of DRAM refresh to use in Suspend mode.
These bits should not be changed while suspend mode is active.
n/a
00
01
10
11
00
01
1X
Table 8-10: Suspend Refresh Selection
Table 8-9: PCLK Divide Selection
n/a
CAS-before-RAS
LCD Power
Disable
MCLK: PCLK Frequency Ratio
CAS-before-RAS (CBR) refresh
DRAM Refresh Type
Suspend
Refresh
Select Bit 1
refresh cycles.
Self-Refresh
No Refresh
1: 1
2: 1
3: 1
4: 1
Epson Research and Development
Suspend
Refresh
Select Bit 0
Hardware Functional Specification
Vancouver Design Center
Issue Date: 99/05/18
Software
Suspend
Mode Enable
RW
Related parts for sed1355
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
SE-BGG729, E-Tec lead free prototype socket drawing for BGG729 and BGG729 packages
Manufacturer:
ACTEL [Actel Corporation]
Datasheet:
Part Number:
Description:
SE-CSG128-H, E-Tec lead free prototype socket drawing for CSG128 and CSG128 packages
Manufacturer:
ACTEL [Actel Corporation]
Datasheet:
Part Number:
Description:
Manufacturer:
ETC-unknow
Datasheet:
Part Number:
Description:
Manufacturer:
ETC-unknow
Datasheet: