sed1355 ETC-unknow, sed1355 Datasheet - Page 90

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

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SED1355
X23A-A-001-11
Symbol
t5a
t5b
t8a
t8b
t10
t11
t12
t13
Ts
t1
t4
t5
t5
t8
t8
t1
t2
t3
t4
t6
t7
t9
min
min
min
min
min
min
Sync Timing
Data Timing
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
= t4
= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts
= [((REG[05h] bits [4:0]) + 1)*8 - 27] Ts
= [((REG[05h] bits [4:0]) + 1)*8 - 29] Ts
= [((REG[05h] bits [4:0]) + 1)*8 - 20] Ts
= [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts
FPFRAME setup to FPLINE pulse trailing edge
FPFRAME hold from FPLINE pulse trailing edge
FPLINE pulse width
FPLINE period
FPSHIFT2 falling edge to FPLINE pulse leading edge
FPSHIFT falling edge to FPLINE pulse leading edge
FPLINE pulse trailing edge to FPSHIFT2 rising, FPSHIFT falling
edge
FPSHIFT2, FPSHIFT period
FPSHIFT falling edge to FPLINE pulse trailing edge
FPSHIFT2 falling edge to FPLINE pulse trailing edge
FPLINE pulse trailing edge to FPSHIFT rising edge
FPSHIFT2, FPSHIFT pulse width high
FPSHIFT2, FPSHIFT pulse width low
UD[3:0], LD[3:0] setup to FPSHIFT2 rising, FPSHIFT falling edge
UD[3:0], LD[3:0] hold from FPSHIFT2 rising, FPSHIFT falling edge
min
- 14Ts
FPSHIFT2
FPFRAME
FPSHIFT
Figure 7-31: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1)
Table 7-26: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1)
FPLINE
FPLINE
UD[3:0]
LD[3:0]
Parameter
t5a
t8b
t5b
t8a
t1
t9
t3
t6
t2
t12
t9 + t10
note 2
note 3
note 4
note 5
note 6
note 7
Min
14
20
9
4
2
2
1
1
1
t4
t13
Epson Research and Development
t10
Typ
Hardware Functional Specification
t7
2
t11
Vancouver Design Center
Max
Issue Date: 99/05/18
Ts (note 1)
Units
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts