ml2722 Sirenza Microdevices, ml2722 Datasheet
ml2722
Available stocks
Related parts for ml2722
ml2722 Summary of contents
Page 1
... The phase locked loop (PLL) synthesizer is completely integrated, including the voltage controlled oscillator (VCO), tuning circuits, and VCO resonator. This allows the ML2722 to be used in frequency hopped spread spectrum (FHSS) applications. The ML2722 contains internal voltage regulation. It also contains PLL and transmitter configuration registers. ...
Page 2
... TABLE OF CONTENTS GENERAL DESCRIPTION ........................................................................................................................................... 1 PIN CONFIGURATION ................................................................................................................................................. 1 ORDERING INFORMATION ........................................................................................................................................ 1 FEATURES ................................................................................................................................................................... 1 APPLICATIONS ............................................................................................................................................................ 1 BLOCK DIAGRAM ........................................................................................................................................................ 1 TABLE OF CONTENTS ................................................................................................................................................ 2 SIMPLIFIED APPLICATIONS DIAGRAM ..................................................................................................................... 3 ELECTRICAL CHARACTERISTICS............................................................................................................................. 4 PIN DESCRIPTIONS.................................................................................................................................................... 7 FUNCTIONAL DESCRIPTION ................................................................................................................................... 13 MODES OF OPERATION........................................................................................................................................... 15 CONTROL INTERFACES........................................................................................................................................... 18 CONTROL INTERFACES AND REGISTER DESCRIPTIONS................................................................................... 20 PHYSICAL DIMENSIONS (INCHES/MILLIMETERS) ................................................................................................ 27 WARRANTY................................................................................................................................................................ 28 DS2722-F-06 FINAL DATASHEET ML2722 DECEMBER 2005 2 ...
Page 3
... ML2722 RRFI MATCHING NETWORK IMAGE REJECT MIXER PAON, TPC 2 TRFO QUADRATURE FILTER DIVIDE BY 2 1.83GHz VCO TX RF BUFFER Figure 1. Simplified Application Diagram FINAL DATASHEET ML2722 DOUT IF DEMOD CIRCUITS RSSI REF BASEBAND CLK, DATA PLL XCEN, RXON 2 CONTROL LOGIC DIN TX DATA ...
Page 4
... PLL main divider input is at 1.83GHz PLL divider limits From RXON asserted From EN asserted, any channel change in 902 to 928MHz band From XCEN, PLL dividers programmed 6.144 or 12.288MHz sine wave, capacitively coupled FINAL DATASHEET ML2722 MIN TYP MAX UNITS μA 10 100 ...
Page 5
... GFSK, BT=0.5, PRBS data -80dBm wanted signal, AM modulation depth at 100kHz rate 20pF load, 20% to 80% 20pF load, 20% to 80% -15dBm in No signal Sensitivity is >50% mid range Sensitivity is >50% mid range Measured at -40dBm input power FINAL DATASHEET ML2722 17-j50 Ω 1.536 Mbps -95 dBm 770 kHz 8 ...
Page 6
... Typical value assumes 3.3V VDD Sinking 0.1mA Time from RXON low to PAON high Time from RXON high to receiver enabled Time from write to PLL tuning register (EN high) to receiver enabled From XCEN high to receiver enabled with continuous reference applied FINAL DATASHEET ML2722 -4.5 -1.0 +2.0 dBm 14 dB 400 460 560 ...
Page 7
... DC power supply input to voltage Regulators and unregulated loads. VCC5 is the main (or master) analog VCC pin. There must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator. DC ground to IF, Demodulator, and Data Slicer circuits. FINAL DATASHEET ML2722 DIAGRAM DECEMBER 2005 7 ...
Page 8
... Receive RF Input. Nominal impedance at 902 to 928MHz is 17-50j Ω with a simple matching network required for optimum noise figure. This input is to the base of an NPN transistor and should be AC coupled. FINAL DATASHEET ML2722 VCC5 24 0.7V 4k RRFI 21 (PIN 8) VSS ...
Page 9
... A CMOS level output (VSS to VDD) with controlled slew rates. A low drive output designed to drive a PCB trace and a CMOS logic input while generating minimal RFI. In digital test modes this pin becomes a test access port controlled by the serial control bus. FINAL DATASHEET ML2722 VCC5 24 23 TRFO Ω 13 12mA ...
Page 10
... Enables the off-chip PA at the correct times in a Transmit slot. Goes high when transmit RF is present at TRFO; goes low 5μs before transmit RF is removed from TRFO. Has interlock logic to shut down the PA if the PLL does not lock. FINAL DATASHEET ML2722 VDD 31 XCEN 1 RXON 2 ...
Page 11
... This is a self-biased CMOS input that is designed to be driven either by an AC-coupled sine wave. Charge Pump Output of the phase detector. This is connected to the external PLL loop filter. FINAL DATASHEET ML2722 TPQ MUX VDD 31 TPC TPC 7 TPC/TPQ MUX Ω ...
Page 12
... CMOS input, and the thresholds are referenced to VDD and VSS. Serial control bus data is clocked in on the rising edge when EN is low. This is a CMOS input; the thresholds are referenced to VDD and VSS. FINAL DATASHEET ML2722 VCC2 VCC2 13 13 1.25V 1.25V ...
Page 13
... It also contains internal voltage regulators to protect critical circuits from power supply noise and transmit modulation circuits. The ML2722 is designed to transmit and receive 1.536M chips per second in 2.048MHz spaced channels in the 902 to 928MHz ISM band. A single synthesizer is used for both the receiver and the FSK transmitter. The phase locked loop (PLL) is completely integrated, including the voltage controlled oscillator (VCO), tuning circuits, and VCO resonator ...
Page 14
... COUNTER DETECTOR LO CHARGE PRESCALER PUM 1.83G Hz VCO I Q QUADRATURE DIVIDE GND VTUNE Figure 2. ML2722 Block Diagram FINAL DATASHEET VCC2 RVCC7 29 13 DATA DATA FILTER SLICER FILTER TEST M UX ALIG N ADDRESS DECODE LO 6-BIT SWALLOW CONTROL COUNTER ...
Page 15
... TDD operation. Prior to transmitting or receiving, time should be allowed for the PLL to lock up and for the filters to be aligned. When the ML2722 is operated in single-carrier TDD mode, the LO is automatically shifted by the second (low) IF frequency when the device is switched between RECEIVE and TRANSMIT modes ...
Page 16
... Transmit data low pass filter bandwidth TRANSMIT MODE In TRANSMIT mode, the VCO is directly modulated with filtered FSK transmit data. The ML2722 transmitter is a 2-FSK transmitter using a directly modulated open loop VCO. The ML2722 design supports transmit time slot lengths up to 10ms, and the time required to set up the transmitter for a new time slot (TXCAL mode) is 62.5µs.This type of transmitter is simple, low power, and well suited to a time-time slotted system ...
Page 17
... The filter alignment registers are reset at power up. TEST MODE The RF to digital functionality of the ML2722 requires special test mode circuitry for IC production test and radio debugging. A test register, available via the 3-wire serial interface, controls the test multiplexers. DS2722-F-06 ...
Page 18
... PAON: SERIAL INTERFACE A 3-wire serial interface (EN, DATA, CLK) is used for programming the ML2722 configuration registers, which control device mode, pin functions, PLL and reference dividers, internal test modes, and filter alignment. Data words are entered beginning with the MSB (“big-endian”). The word is divided into a leading 14-bit data field followed by a 2-bit address field ...
Page 19
... Clock period Minimum pulse width Delay from last clock falling edge Enable setup time to ignore next rising clock Data-to-clock setup time Data-to-clock hold time Table 3. 3-Wire Bus Timing Characteristics DB11 DB0 FINAL DATASHEET ML2722 TIME (ns >50 2000 >15 >15 >15 > ...
Page 20
... A unidirectional 3-wire serial bus sets the ML2722’s transceiver parameters and programs the PLL circuits. Programming is performed by entering 16-bit words into the ML2722 serial interface. Three 16-bit registers are partitioned such that 14 bits are dedicated for data to program the operation and two bits identify the register address. ...
Page 21
... Table 4. Register 0 -- PLL Configuration Register DESCRIPTION Channel Frequency select bits MSB Address Bit ADR1 = 0 LSB Address Bit ADR0 = 1 Table 5. Register 1 – Channel Frequency Register FINAL DATASHEET ML2722 USE Set all bits to 0 (zero) USE Set all bits to 0 (zero) Divide ratio = f / 0.512 c DECEMBER 2005 ...
Page 22
... The 16 bits are input serially (see Figure 5) with the 14 data bits, most significant bit (DB13) first followed by the two address bits, most significant bit (ADR1) first. The last 16 bits clocked into the ML2722 will be loaded into the specified register. Loading less than 16 bits into any register will cause unpredictable device functionality. ...
Page 23
... NOMINAL REFERENCE FREQUENCY 6 12 Table 8. Reference Frequency Select RXCL RECEIVE PLL MODE 0 PLL open loop 1 PLL closed loop Table 9. PLL Mode in Normal Receive Operation LO SHIFT FOR TRANSMIT LO SHIFT FOR RECEIVE 0 +1.024MHz Table 10. PLL Frequency Shift FINAL DATASHEET ML2722 6.144MHz 12.288MHz +1.024MHz 0 DECEMBER 2005 23 ...
Page 24
... Table 11. PLL Mode in Transmit Operation TPC TPC PIN STATE 0 High Impedance 1 Pulled to Ground Table 12. TPC Pin State C B15 B14 B13 PLL divide ratio 0 Table 13. Main Divider FINAL DATASHEET ML2722 /0.512, where f is the channel frequency DECEMBER 2005 24 ...
Page 25
... REGISTER #2, FILTER TUNING SELECT TEST MODE Analog Test Control Bits (ATM): <DB2:DB0> The test mode selected is described in Table 14. The performance of the ML2722 is not specified in these test modes. Although primarily intended for IC test and debug, they also can help in debugging the radio system. The default (power-up) state of these bits is ATM< ...
Page 26
... ML2722 falls below 2.6V. The PLL lock detect or low voltage signals are latched, so that the transmitter is inhibited for the entire transmit time slot. These latches are reset at the end of the transmit time slot, so that the ML2722 will transmit in the next time slot following a transient fault condition. ...
Page 27
... The package pins are finished with 100% matte tin. DS2722-F-06 Package: 32-Pin ( 1mm) 25 0.276 BSC 0.354 BSC (7.00 BSC) (9.00 BSC) 17 0.048 MAX 0.012 - 0.018 (1.20 MAX) (0.29 - 0.45) 0.037 - 0.041 (0.95 - 1.05) Leads cannot exceed 0.004 maximum coplanarity (0.102) FINAL DATASHEET ML2722 0º - 8º 0.003 - 0.008 (0.09 - 0.20) 0.018 - 0.030 (0.45 - 0.75) SEATING PLANE DECEMBER 2005 27 ...
Page 28
... Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. DS2722-F-06 Micro Linear Corporation 2050 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com FINAL DATASHEET ML2722 DECEMBER 2005 28 ...