D485505G NEC [NEC], D485505G Datasheet
D485505G
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D485505G Summary of contents
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... Part Number R/W Cycle Time PD485505G- PD485505G- The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information ...
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... OUT3 RE 5 RSTR 6 GND 7 RCK OUT4 D 10 OUT5 D 11 OUT6 D 12 OUT7 Remark Refer to 5. Package Drawing for the 1-pin index mark PD485505G Data Inputs IN0 IN7 Data Outputs OUT0 OUT7 WCK ...
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Block Diagram WCK D IN0 D IN1 D IN2 D IN3 D IN4 D IN5 D IN6 D IN7 WE RSTR Write Address Pointer Memory Cell Array 40,384 bits (5,048 words by 8 bits) Read Address Pointer Data Sheet M10059EJ7V0DS00 ...
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Input/Output Pin Function Pin I/O Pin Pin Symbol Number Name Data IN0 | Input IN7 Out Data OUT0 | Output OUT7 19 ...
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Operation Mode PD485505 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK). For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK). ...
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Operation-related Restriction Following restriction exists to read data written in a write cycle. Read the written data after an elapse of 1/2 write cycle + not satisfied, the output data may undefined. WAR Figure 2.1 Delay ...
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Electrical Specifications All voltages are referenced to GND. Absolute Maximum Ratings Parameter Voltage on any pin relative to GND Supply voltage Output current Operating ambient temperature Storage temperature Note –3.0 V MIN. (Pulse width = 10 ns) Caution Exposing ...
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AC Characteristics (Recommended Operating Conditions unless otherwise noted) Parameter Write clock cycle time Write clock pulse width Write clock precharge time Read clock cycle time Read clock pulse width Read clock precharge time Access time Write data-read delay time Output ...
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Notes 1. AC measurements assume Characteristics test condition Input Timing Specification 3 Output Timing Specification High impedance Output Loads for Timing OUT 1 Input timing reference ...
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Write Cycle Timing Chart Cycle n Cycle n+1 t WCK t WCP WCK (Input) t WCW WE (Input (Input) (n) IN Remark RSTW = “H” level Read Cycle Timing Chart Cycle n Cycle n+1 t ...
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Write Reset Cycle Timing Chart (WE = Active) Cycle n WCK (Input RN1 RS RSTW (Input) WE (Input) “L” Level t DS (n–1) D (Input) IN Note In write reset cycle, reset operation is executed even without a ...
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Read Reset Cycle Timing Chart (RE = Active) Cycle n RCK (Input RN1 RSTR (Input) RE (Input) “L” Level t AC (n–1) D (Output) (n) OUT Note In read reset cycle, reset operation is executed even without ...
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Application 4 Delay Line PD485505 easily allows (5,048 bits) delay line (see Figure 4.1). Figure 4 Delay Line Circuit 40 MHz Clock WCK Data Input Figure 4 ...
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Bit Delay It is possible to make delay read from the write data with the PD485505. (1) Perform a reset operation in the cycle proportionate to the delay length. (Figure 4.3) (2) Shift the input timing of write ...
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Figure 4.4 n-Bit Delay Line Timing Chart (2) t WCK t RCK Cycle 0 Cycle 1 Write Read t t WCW WCP t t RCW RCP WCK/RCK (Input RSTW (Input) RSTR t DS (Input ...
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Double-speed Conversion Figure 4.6 shows an example timing chart of double-speed and twice reading operation (f 2 cycle) for a write operation (f = 5,048 cycle). W Caution The read operation collide with the write operation on the same ...
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Package Drawing 24-PIN PLASTIC SOP (11.43 mm (450 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 13 detail of ...
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... Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the PD485505. Type of Surface Mount Device PD485505G: 24-pin plastic SOP (11.43 mm (450)) 7. Example of Stamping Letter E in the fifth character position in a lot number signifies version E, letter K, version K, letter P, version P, and letter L, version L. ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date ...