UPD70325L-8 NEC, UPD70325L-8 Datasheet

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UPD70325L-8

Manufacturer Part Number
UPD70325L-8
Description
16/8 bit single-chip microcomputer
Manufacturer
NEC
Datasheet
Document No. U12850EJ7V0DS00 (7th edition)
Date Published November 1997 N
Printed in Japan
controller, interrupt controller, etc. are all integrated. The PD70325 is software compatible with the 16/8-bit single-
chip microcontroller PD70320 (V25
to the V25.
FEATURES
The PD70325 (V25+) is a single-chip microcontroller on which 16-bit CPU, RAM, serial interface, timer, DMA
Software compatible with V25
Software compatible with PD70108/70116 (in native mode) (some instructions added)
Internal 16-bit architecture and external 8-bit data bus
3-stage pipeline method
Minimum instruction cycle : 250 ns/8 MHz (external 16 MHz)
Memory space 1 Mbyte
On-chip RAM : 256 words
Register bank (memory mapped method) : 8 banks
Input port (port T) with comparator : 8 bits
I/O lines (input port : 4 bits, input/output ports : 20 bits)
Serial interface : 2 channels
• Internal dedicated baud rate generator
• Asynchronous mode and I/O interface mode
Interrupt controller
• Programmable priority (8 levels)
• 3 types of interrupt response method
DRAM and pseudo SRAM refreshing function
DMA controller : 2 channels
• 4 types of DMA transfer mode
• Transfer rate
• Address pointer (linear) : 20 bits
• Terminal counter : 16 bits
16-bit timer : 2 channels
Time base counter (20 bits) : 1 channel
On-chip clock generator
Programmable wait function
Standby function (STOP, HALT)
Vectored interrupt function, register bank switching function, macro service function
Maximum 4 Mbytes/second (when stop control is not executed by DMARQ pin in demand release
mode)
Maximum 2 Mbytes/second (when stop control is executed by DMARQ pin in demand release
mode, or burst mode)
16/8-BIT SINGLE-CHIP MICROCONTROLLER
The information in this document is subject to change without notice.
: 200 ns/10 MHz (external 20 MHz)
8 bits
TM
). The V25+ greatly improves the DMA responsivity and transfer rate compared
The mark
DATA SHEET
shows major revised points.
V25+
TM
MOS INTEGRATED CIRCUIT
PD70325
©
1996
1995

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UPD70325L-8 Summary of contents

Page 1

SINGLE-CHIP MICROCONTROLLER The PD70325 (V25 single-chip microcontroller on which 16-bit CPU, RAM, serial interface, timer, DMA controller, interrupt controller, etc. are all integrated. The PD70325 is software compatible with the 16/8-bit single- chip microcontroller PD70320 (V25 to ...

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ORDERING INFORMATION Part Number PD70325GJ-8-5BG 94-pin plastic QFP (20 PD70325GJ-10-5BG 94-pin plastic QFP (20 PD70325L-8 84-pin plastic QFJ (1150 PD70325L-10 84-pin plastic QFJ (1150 2 Package External Clock (MHz) 20 mm) 20 mm) 1150 mil) 1150 mil) PD70325 16 20 ...

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... Execution format in single-step mode 1 DMA transfer/1 instruction execution DMA Interrupt request during DMA transfer Accepts only NMI function (demand release mode) Number of necessary waits when stop is controlled by DMARQ (demand release mode) Transfer processing units TC (terminal counter) setting value Generation timing of terminal counter ...

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... A19 9 RxD0 10 GND 11 CTS0 12 TxD0 13 RxD1 14 CTS1 15 TxD1 16 P20/DMARQ0 P21/DMAAK0 P22/TC0 Remarks Non-Connection Internally Connected Cautions 1. Fix IC pin individually to high level via a pull-up resistor externally. 2. Fix EA pin to low level PD70325 71 P05 P04 67 P03 66 P02 65 P01 64 P00 MREQ 61 IOSTB 60 MSTB 59 R/W 58 REFRQ ...

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... PD70325L- P07/CLKOUT A10 31 A11 Remark IC: Internally Connected Cautions 1. Fix IC pin individually to high level via a pull-up resistor externally. 2 Fix EA pin to low level PD70325 74 PT7 73 PT6 72 PT5 71 PT4 70 PT3 69 PT2 68 PT1 67 PT0 66 P17/READY 65 P16/SCK0 64 P15/TOUT 63 P14/INT/POLL 62 P13/INTP2/INTAK 61 P12/INTP1 60 P11/INTP0 59 NMI (P10) 58 P27/HLDRQ 57 P26/HLDAK ...

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P20/DMARQ0 LC P21/DMAAK0 PROGRAMMABLE etc. P22/TC0 DMA P23/DMARQ1 CONTROLLER P24/DMAAK1 PSW P25/TC1 PC TxD0 SERIAL RxD0 INTERFACE P16/SCK0 CTS0 TxD1 BAUD RATE RxD1 GENERATOR CTS1 NMI (P10) PROGRAMMABLE P11/INTP0 INTERRUPT P12/INTP1 P13/INTP2/INTAK CONTROLLER P14/INT/POLL TIME BASE 16-BIT TIMER COUNTER TOUT/P15 ...

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PIN FUNCTIONS .................................................................................................................................. 8 1.1 Port Pins ....................................................................................................................................................... 8 1.2 Non-port Pins ............................................................................................................................................... 9 2. INSTRUCTION SETS ......................................................................................................................... 10 2.1 Comparison between PD70108 and 70116 ........................................................................................... 10 2.2 Instruction Set Operation ......................................................................................................................... 12 2.3 Instruction Set Table ................................................................................................................................. 16 ...

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PIN FUNCTIONS 1.1 Port Pins Pin Name Input/Output P00 to P06 Input & output P07/CLKOUT Input & output/output NMI (P10) Input P11/INTP0 P12/INTP1 P13/INTP2/INTAK Input/input/output P14/POLL/INT Input & output/input/input P15/TOUT Input & output/output P16/SCK0 P17/READY Input & output/input P20/DMARQ0 ...

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... Memory read/memory write strobe output R/ W Read cycle/write cycle ID signal output IOSTB I/O read/ I/O write strobe output V Positive power supply pins (all pins should be connected) DD GND GND pins (all pins should be connected) IC Internally connected (fix to high level via a pull-up resistor externally) PD70325 Function 9 ...

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INSTRUCTION SETS The PD70325 instruction sets are compatible with those of PD70320. 2.1 Comparison between PD70108 and 70116 The PD70325 instruction sets are upward-compatible with those of PD70108/70116 in native mode. The following instructions are newly added to the ...

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Register bank switch instructions • BRKCS ······ Used to switch register banks A register bank is switched to the register bank indicated by the lower 3 bits in the 16-bit register described in the operand. The program is also ...

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Instruction Set Operation Identifier reg, reg’ 8-/16-bit general register reg8, reg8’ 8-bit general register reg16, reg16’ 16-bit general register dmem 8-/16-bit memory location mem 8-/16-bit memory location mem8 8-bit memory location mem16 16-bit memory location mem32 32-bit memory location ...

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Table 2-2. Operation Code Identifier Identifier W Byte/word specification bit (0: byte, 1: word). However, when the sign extended byte data should be 16-bit operand even when reg, reg’ Register field (000 to 111) ...

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Table 2-3. Operation Identifier (2/2) Identifier temp Temporary register (8/16/32 bits) tmpcy Temporary carry flag (1 bit) seg Immediate segment data (16 bits) offset Immediate offset data (16 bits) Transfer direction + Addition – Subtraction Multiplication Division % Modulo AND ...

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Table 2-6. 8/16-Bit General Register Selection reg, reg’ 000 AL 001 CL 010 DL 011 BL 100 AH 101 CH 110 DH 111 BH Table 2-7. Segment Register Selection sreg 00 DS1 ...

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Operation Code Group Mnemonic Operand Data reg,reg’ reg reg’ MOV transfer mem,reg 1 0 ...

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Operation Code Group Mnemonic Operand Repeat REPC prefix REPNC ...

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Operation Code Group Mnemonic Operand reg8,reg8’ Bit field ...

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Operation Code Group Mnemonic Operand reg,reg’ reg Addi- ADD tion/ subtrac- mem,reg 0 0 ...

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Operation Code Group Mnemonic Operand BCD ADD4S opera- ...

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Operation Code Group Mnemonic Operand Multipli- reg8 reg MULU cation mem8 ...

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Operation Code Group Mnemonic Operand Unsign- DIVU reg8 reg ed division ...

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Operation Code Group Mnemonic Operand Signed reg8 reg DIV division mem8 ...

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Operation Code Group Mnemonic Operand BCD ADJBA adjust- ment ...

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Operation Code Group Mnemonic Operand Logical reg,reg’ reg’ TEST opera- mem,reg tion 1 0 ...

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Operation Code Group Mnemonic Operand Bit TEST1 reg8, reg manipu- lation ...

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Operation Code Group Mnemonic Operand Bit CLR1 reg8, reg manipu- lation ...

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Operation Code Group Mnemonic Operand Shift SHL reg reg mem,1 1 ...

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Operation Code Group Mnemonic Operand Shift SHR reg reg mem,1 1 ...

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Operation Code Group Mnemonic Operand Rotate ROL reg reg mem,1 1 ...

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Operation Code Group Mnemonic Operand Rotate ROLC reg reg mem,1 1 ...

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Operation Code Group Mnemonic Operand Rotate RORC reg reg mem,1 1 ...

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Operation Code Group Mnemonic Operand Sub- CALL near-proc routine control regptr16 ...

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Operation Code Group Mnemonic Operand mem16 mod mem Stack PUSH manipu- lation reg16 ...

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Operation Code Group Mnemonic Operand Condi- short-label tional branch BNV short-label ...

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Operation Code Group Mnemonic Operand Interrupt BRK imm8 ...

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Operation Code Group Mnemonic Operand CPU HALT control ...

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Number of Clocks Table (1) Legend The number of clocks, for memory operand, differs among addressing modes. So, use the following values for “EA” items shown in Table 2-9 Number of Clocks. Table 2-8. Number of Clocks for Each ...

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Number of clocks Table 2-9. Number of Clocks (1/10) Group Mnemonic Operands Data MOV reg, reg’ transfer mem, reg reg, mem mem, imm reg, imm acc, dmem dmem, acc sreg, reg16 sreg, mem16 reg16, sreg mem16, sreg DS0, reg16, ...

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Group Mnemonic Operands Primitive CMPM Note 1 dst-block block src-block Note 2 transfer LDM Note 1 src-block Note 2 Note 1 STM dst-block Note 2 Bit field INS reg8, reg8’ manipula- reg8, imm4 tion EXT reg8, reg8’ reg8, imm4 I/O ...

Page 41

Table 2-9. Number of Clocks (3/10) Group Mnemonic Operands Addition/ SUB reg, reg’ subtraction mem, reg reg, mem reg, imm mem, imm acc, imm SUBC reg, reg’ mem, reg reg, mem reg, imm mem, imm acc, imm BCD ADD4S Note ...

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Group Mnemonic Operands Multiplica- MUL reg8 tion mem8 reg16 mem16 reg16, (reg16’,) imm8 reg16, mem16, imm8 reg16, (reg16’,) imm16 reg16, mem16, imm16 Unsigned DIVU reg8 division mem8 reg16 mem16 Signed DIV reg8 division mem8 reg16 mem16 BCD ADJBA adjustment ADJ4A ...

Page 43

Table 2-9. Number of Clocks (5/10) Group Mnemonic Operands Comple NOT reg ment mem operation NEG reg mem Logical TEST reg, reg’ operation mem, reg/ reg, mem reg, imm mem, imm acc, imm AND reg, reg’ mem, reg reg, mem ...

Page 44

Group Mnemonic Operands Bit NOT1 mem16, CL manipula- reg8, imm3 tion mem8, imm3 reg16, imm4 mem16, imm4 NOT1 CY Bit CLR1 reg8, CL manipula- mem8, CL tion reg16, CL mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 SET1 ...

Page 45

Table 2-9. Number of Clocks (7/10) Group Mnemonic Operands Shift SHR reg, CL mem, CL Note reg, imm8 mem, imm8 SHRA reg,1 mem, 1 reg, CL mem, CL Note reg, imm8 mem, imm8 Rotate ROL reg,1 mem, 1 reg, CL ...

Page 46

Group Mnemonic Operands Rotate RORC reg, CL mem, CL Note 1 reg, imm8 mem, imm8 Subroutine CALL near-proc control regptr16 memptr16 far-proc memptr32 RET pop-value pop-value Stack PUSH mem16 manipula- reg16 tion sreg PSW R imm8 imm16 POP mem16 reg16 ...

Page 47

Table 2-9. Number of Clocks (9/10) Group Mnemonic Operands Branch BR near-label short-label regptr16 memptr16 far-label memptr32 Conditional BV short-label Note branch BNV short-label BC/BL short-label BNC/BNL short-label BE/BZ short-label BNE/BNZ short-label BNH short-label BH short-label BN short-label BP short-label ...

Page 48

Table 2-9. Number of Clocks (10/10) Group Mnemonic Operands Register BRKCS reg16 bank switch TSKSW reg16 CPU HALT control STOP POLL DI EI BUSLOCK FPO1 fp-op fp-op, mem FPO2 fp-op fp-op, mem NOP Segment override prefix (DS0:, DS1:, PS: and ...

Page 49

... Output Current High Operating Ambient Temperature Storage Temperature Cautions 1. Do not make direct connections of the output (or input/output) pins of the IC product with each other, and also avoid direct connections to V the open collector pins can be directly connected with each other. For the external circuit designed with the timing specifications so that any collision of the outputs from the pins subject to high-impedance state may be prevented, direct connection can be also made ...

Page 50

OSCILLATOR CHARACTERISTICS PD70325 – PD70325- – Resonator Recommended Circuit Ceramic or Crystal Resonator X1 C1 External Clock 1 X1 HCMOS Inverter HCMOS Inverter ...

Page 51

CAPACITANCE ( Parameter Symbol Input Capacitance C I Output Capacitance C O Input/output Capacitance CHARACTERISTICS PD70325 – PD70325- –10 ...

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Parameter Address Delay Time from CLKOUT Data Input Delay Time from Address Data Delay Time from MREQ Data Delay Time from MSTB MSTB Delay Time from MREQ MREQ Low-Level Width Address Hold Time (from MREQ ) Data Input Hold Time ...

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Parameter READY Hold Time (from MREQ , IOSTB ) HLDRQ Setup Time (to CLKOUT ) HLDAK Delay Time from CLKOUT HLDAK Delay Time from Bus Float Bus Output Delay Time from HLDAK HLDAK Delay Time from HLDRQ Bus Output Delay ...

Page 54

PD70325- – Parameter X1 Input Cycle Time X1 Input High-/Low-Level Width X1 Input Rise/Fall Time CLKOUT Output Cycle Time CLKOUT Output High-/Low-Level Width t CLKOUT Output Rise/Fall Time Input Rise/Fall Time Output ...

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Parameter RESET Low-Level Width READY Setup Time (to MREQ , IOSTB ) READY Hold Time (from MREQ , IOSTB ) HLDRQ Setup Time (to CLKOUT ) HLDAK Delay Time from CLKOUT HLDAK Delay Time from Bus Float Bus Output Delay ...

Page 56

COMPARATOR CHARACTERISTICS PD70325 – PD70325- – Parameter Symbol Comparator Accuracy V ACOMP Threshold Voltage V TH Compare Time t COMP PT Input Voltage V IPT DATA ...

Page 57

DATA HOLDING TIMING t FVD AC TEST INPUT WAVEFORM (Except RESET, NMI, X1 and X2) 2 TEST INPUT WAVEFORM (RESET, NMI, X1 and X2 IFS AC TEST OUTPUT ...

Page 58

CLOCK TIMING CLKOUT t KR POLL INPUT TIMING CLKOUT t SPLK POLL CTS0 AND CTS1 INPUT TIMING CTS0 and CTS1 58 t CYX t t WXH WXL CYK t t WKH WKL t KF ...

Page 59

INTERRUPT INPUT/DMA INPUT TIMING CLKOUT NMI t SIQK Note Note INTP0 to INTP2, DMARQ0 to DMARQ1 RESET INPUT TIMING When STOP mode is released/at power-on reset: Hi-Z Note CLKOUT t WRSL1 RESET Note CLKOUT signal is output after CLKOUT output ...

Page 60

... HCRY1 t SCRY t SCRY0 READY Notes 1. In case of memory cycle 2. In case of I/O cycle Caution The wait state insertion by the external READY signal is necessary to make the value of wait control register (WTC) “11” (2 waits + insertion state by READY pin). 60 TAW TAW 3]: TAW TW PD70325 T2 (n – ...

Page 61

SERIAL OPERATION When transmitting data in I/O interface mode SCK0 TxD When receiving data in I/O interface mode CTS0 RxD t CYTK t t WSTL WSTH t DTKD t CYRK t t WSRL WSRH t SRDK t HKRD PD70325 t ...

Page 62

READ OPERATION t CYK CLKOUT t DKA A19 Hi R/W t DAMR MREQ MSTB t DAMS IOSTB REFRQ DMAAK1 to DMAAK0 62 t DKA t DADR HMA t DMRD t HMDR t t WMRL ...

Page 63

WRITE OPERATION t CYK CLKOUT t DKA A19 DADW Hi DAMR MREQ MSTB t DAMS IOSTB REFRQ DMAAK1 to DMAAK0 t DKA t HMA Hi-Z t SDM t HMDW t t ...

Page 64

I/O READ TIMING t CYK CLKOUT t DKA A19 DADR Hi MREQ H MSTB t DAIS IOSTB REFRQ DMAAK1 to DMAAK0 64 t DKA t HISA t DISD t HISDR t t ...

Page 65

I/O WRITE TIMING t CYK CLKOUT t DKA A19 DADW Hi MREQ H MSTB t DAIS IOSTB REFRQ DMAAK1 to DMAAK0 t DKA t HISA Hi-Z t SDIS t HISDW t t ...

Page 66

DMA (I/O MEMORY) TIMING t CYK CLKOUT t DKA A19 R/W t DAMR MREQ MSTB t DAMS IOSTB DMARQ1 to DMARQ0 DMAAK1 to DMAAK0 TC1 to TC0 66 Hi WMRL HMA t t ...

Page 67

DMA (MEMORY I/O) TIMING t CYK CLKOUT t DKA A19 R/W t DAMR MREQ MSTB t DAMS IOSTB DMARQ1 to DMARQ0 DMAAK1 to DMAAK0 TC1 to TC0 Hi WMRL HMA t RVC t ...

Page 68

REFRESH TIMING t CYK CLKOUT t DKA A19 MREQ H MSTB IOSTB t DARF REFRQ DMAAK1 to DMAAK0 68 Hi WRFL HRFA t RVC PD70325 ...

Page 69

HOLD REQUEST/ACKNOWLEDGE TIMING Normal mode CLKOUT t SHQK HLDRQ Note HLDAK Releasing HOLD mode at refreshing time CLKOUT HLDRQ Note t DKHA HLDAK Note A19 to A0 D0, MREQ, MSTB, IOSTB, R/W EXTERNAL INTERRUPT REQUEST/ACKNOWLEDGE TIMING CLKOUT t ...

Page 70

... The V25 Family is designed to create access signals to memory and I/O, based on the MREQ signal and IOSTB signal. When V25 Family products are connected with memory and I/O, design is possible even if there are no AC characteristics based on the clock. The clock synchronization timing shown below is for executing accurate READY input control using the system clock ...

Page 71

READY TIMING When 2 wait states are inserted: T1 CLKOUT A19 to A0 MREQ IOSTB t SRYK READY When 1 extra wait state is inserted: T1 CLKOUT A19 to A0 MREQ IOSTB t SRYK READY TAW TAW t HKRY TAW ...

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MEMORY READ OPERATION t CYK CLKOUT t DKA A19 R/W MREQ MEMORY WRITE OPERATION t CYK CLKOUT t DKA A19 R/W MREQ 72 t DKA t HKD t ...

Page 73

I/O READ TIMING CLKOUT A19 R/W MREQ IOSTB I/O WRITE TIMING CLKOUT A19 R/W MREQ IOSTB t CYK t DKA t t SDK HKD t t DKIS DKIS ...

Page 74

PACKAGE DRAWINGS 94 PIN PLASTIC QFP ( 20 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition ...

Page 75

PIN PLASTIC QFJ ( 1150 mil NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition P84L-50A3-2 ...

Page 76

RECOMMENDED SOLDERING CONDITIONS The following conditions must be met when soldering this product. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Please consult with our sales office when using other soldering process or under ...

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PD70325 77 ...

Page 78

... Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices ...

Page 79

... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • ...

Page 80

... Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...

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