MRF24J40-I MICROCHIP [Microchip Technology], MRF24J40-I Datasheet - Page 23

• Manufacturer Part Number: MRF24J40-I
• Manufacturer: MICROCHIP [Microchip Technology]

6.0
6.1
Before the MRF24J40 can be used to transmit and
receive packets, certain device settings must be initial-
ized. Depending on the application, some configuration
options may need to be changed. Normally, these tasks
may be accomplished once after Reset and do not
need to be changed thereafter.
REGISTER 6-1:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TXCRCEN
R/W-0
INITIALIZATION
Overview
TXCRCEN: No CRC Data with Normal FIFO bit
1 = CRC is disabled for the TX FIFO
0 = CRC is enabled for the TX FIFO
Reserved: Maintain as ‘0’
ACKEN: No ACK Respond in Any Case bit
1 = ACK response is always disabled
0 = ACK response enabled. ACKs are returned when they are requested.
Reserved: Maintain as ‘0’
PANCOORD: PAN Coordinator bit
1 = Set as PAN coordinator
0 = Not set as PAN coordinator
COORD: Coordinator bit
1 = Set as coordinator
0 = Not set as coordinator
RXCRCEN: Error Report bit
1 = RX all kinds of PKT (including CRC error)
0 = Only RX PKT (CRC ok)
PROMI: RX All Kinds of PKT bit (CRC ok)
1 = RX all kinds of PKT (CRC ok)
0 = Discard PKT when there is a MAC address mismatch, illegal frame type, dPAN/sPAN or
R/W-0
MAC short address mismatch
RXMCR: RECEIVE FILTER CONTROL REGISTER
r
W = Writable bit
‘1’ = Bit is set
ACKEN
R/W-0
Advance Information
R/W-0
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PANCOORD
R/W-0
6.2
To minimize the processing requirements of the host
controller, the MRF24J40 incorporates several different
receive filters which can automatically reject packets
which are not needed. These options are controlled
through the RXMCR register.
Receive Filters
COORD
R/W-0
x = Bit is unknown
MRF24J40
RXCRCEN
R/W-0
DS39776A-page 21
PROMI
R/W-0
bit 0