MRF24J40-I MICROCHIP [Microchip Technology], MRF24J40-I Datasheet - Page 62

• Manufacturer Part Number: MRF24J40-I
• Manufacturer: MICROCHIP [Microchip Technology]

MRF24J40
PCB Antenna
PHY Initialization ................................................................ 22
Pin Descriptions ................................................................... 5
Power-Saving Mode ............................................................. 3
Proprietary Protocols ............................................................ 1
R
Reader Response .............................................................. 62
Receive Buffers .................................................................... 9
Receive Filters ................................................................... 21
Receive Packets ................................................................ 21
Receive Process Flowchart ................................................ 32
Receiving Packets .............................................................. 31
Recommended Operating Conditions ................................ 42
Reference Clock Output ....................................................... 3
Register File Summary ....................................................... 11
Registers
DS39776A-page 60
Dimensions ................................................................ 49
Simulation Results ..................................................... 50
CLKOUT (Clock Output) .............................................. 5
CS (Serial Interface Enable) ........................................ 5
GND (Ground, Digital Circuit) ...................................... 5
GND (Ground, PLL) ..................................................... 5
GND (Guard Ring Ground) .......................................... 5
GPIO0 (External PA Enable) ....................................... 5
GPIO1 (External TX/RX Switch Control) ...................... 5
GPIO2 (External TX/RX Switch Control) ...................... 5
GPIO3 (General Purpose Digital I/O) ........................... 5
GPIO4 (General Purpose Digital I/O) ........................... 5
GPIO5 (General Purpose Digital I/O) ........................... 5
INT (Interrupt Pin) ........................................................ 5
LCAP (PLL Loop Filter External Capacitor) ................. 5
LPOSC1 (32 kHz Crystal Input) ................................... 5
LPOSC2 (32 kHz Crystal Input) ................................... 5
NC (No Connection) ..................................................... 5
OSC1 (20 MHz Crystal Input) ...................................... 5
OSC2 (20 MHz Crystal Input) ...................................... 5
RESET (Global Hardware Reset Active-Low) .............. 5
RFN (Differential RF Pin, Negative) ............................. 5
RFP (Differential RF Pin, Positive) ............................... 5
RXIP (Analog RX I Channel Output) ............................ 5
RXQP (Analog RX Q Channel Output) ........................ 5
SCK (Serial Interface Clock) ........................................ 5
SDI (Serial Interface Data Input) .................................. 5
SDO (Serial Interface Data Output) ............................. 5
V
V
V
V
V
V
V
V
WAKE (External Wake-up Trigger) .............................. 5
MiWi ............................................................................. 1
ZigBee ...................................................................... 1, 9
Freeing Buffer Space ................................................. 34
Layout ........................................................................ 33
BBREG2 (Baseband CCA/RSSI Mode 2) .................. 25
BBREG6 (Baseband RSSI Mode 6) .......................... 25
CLKCTRL (Divided Sleep Clock Selection) ................. 7
CLKINTCR (SLPCLK On/Off and
GPIO (GPIO Port) ...................................................... 39
INTMSK (Interrupt Mask) ........................................... 37
DD
DD
DD
DD
DD
DD
DD
DD
(Charge Pump Power Supply) .............................. 5
(Digital Circuit Power Supply) ............................... 5
(Guard Ring Power Supply) .................................. 5
(PLL Power Supply) .............................................. 5
(Power Supply, Analog Circuit) ............................. 5
(Power Supply, Band Gap
(RF Power Supply) ............................................... 5
(VCO Supply) ....................................................... 5
Reference Circuit) ................................................ 5
Interrupt Polarity) ............................................... 38
Advance Information
RF Measurements ............................................................. 47
RF Output ............................................................................ 8
RF Transceiver .................................................................. 47
RSSI Default Threshold ..................................................... 22
RX FIFO ............................................................................. 31
RX MAC ............................................................................. 31
S
Schematic .......................................................................... 55
Security Buffer ..................................................................... 9
Serial Communications ........................................................ 3
Serial Peripheral Interface (SPI) ........................................ 13
Short Address Register Interface ....................................... 14
Short Address Summary .................................................... 11
Short Addresses ................................................................ 26
Sleep Mode .......................................................................... 3
T
Timing Diagrams
Transmit Buffers .................................................................. 9
Transmit Packets ............................................................... 21
Transmitting Packets ......................................................... 29
TX FIFO ............................................................................. 30
TX FIFO Format ................................................................. 29
TX MAC ............................................................................. 29
W
WWW Address .................................................................. 61
WWW, On-Line Support ...................................................... 2
Z
Zigbee V1.0 Specification .................................................... 9
ISRSTS (Interrupt Status) .......................................... 36
PANIDH (MAC PAN High Byte) ................................. 26
PANIDL (MAC PAN Low Byte) .................................. 26
RFCTL (RF Mode Control) ........................................ 24
RFCTRL0 (RF Control 0) ........................................... 24
RFCTRL2 (RF Control 2) ........................................... 22
RFCTRL3 (RF Control 3) ........................................... 22
RFCTRL6 (RF Control 6) ........................................... 23
RFCTRL7 (RF Control 7) ............................................. 8
RFCTRL8 (RF Control 8) ........................................... 23
RSSITHCCA (RSSI Threshold for CCA) ................... 23
RXFLUSH (Receive FIFO Flush) ............................... 34
RXMCR (Receive Filter Control) ................................ 21
SADRH (MAC Short Address High Byte) .................. 27
SADRL (MAC Short Address Low Byte) .................... 27
TRISGPIO (GPIO Pin Direction
TXNMTRIG (Trigger and Setting
TXSR (TX MAC Status) ............................................. 31
Reading ..................................................................... 14
Writing ....................................................................... 15
Example SPI Slave Mode .......................................... 43
Long Address Read ................................................... 16
Long Address Write ................................................... 17
Short Address Read .................................................. 14
Short Address Write ................................................... 15
SPI Input .................................................................... 13
SPI Output ................................................................. 13
Status ........................................................................ 31
Trigger Packet ........................................................... 30
and SPI Mode) ................................................... 40
for Normal Frame, CAP) .................................... 30
© 2006 Microchip Technology Inc.