ia82527 Innovasic Semiconductor Inc., ia82527 Datasheet - Page 22

• Manufacturer Part Number: ia82527
• Description: Serial Communications Controller?can Protocol
• Manufacturer: Innovasic Semiconductor Inc.

IA82527
CAN Serial Communications Controller
Table 3. Pin/Signal Descriptions (Continued)
reset_n
r-w_n
rx0
rx1
sclk
Signal
wr_n/wrl_n/r-w_n
a6/ad6/sclk
reset_n
Name
rx0
rx1
Pin
PLCC
29
22
21
40
7
PQFP
23
16
15
34
1
IA211080504-02
Page 22 of 53
reset. Input. Active Low. When the reset_n signal is
asserted (low), the IA82527 is initialized. There are
two reset situations:
Cold reset is a power-on reset. As V
valid level (power on), the reset_n signal must be
driven low for a minimum of 1 ms measured from a
valid V
required during a cold reset.
For warm reset, V
power is already on and remains on) while reset_n is
driven low for a minimum of 1 ms.
read-write. Input. Active High (read)-Active Low
(write). Mode 2 and Mode 3. When r-w_n is high, it
signals a read cycle. When r-w_n is low, it signals a
write cycle.
Receive (rx), lines 0 and 1. Input. Pins rx0 and rx1
are the inputs to the IA82527 from the CAN bus lines.
These pins connect internally to the receiver input
comparator. Serial data from the CAN bus can be
received using both rx0 and rx1 or by using only rx0
as follows:
After a cold reset (power on), the default configuration
is the use of both rx0 and rx1 for the CAN bus input.
serial clock. Input. Serial Interface Mode. The sclk
pin is the serial clock input to the IA82527 (slave
device). The clock signal is provided by the master
device.
When the CoBy Bit in the Bus Configuration
Register (2FH) is a 0, rx0 and rx1 are connected to
the input comparator rx0 is connected to the
non-inverting input and rx1 is connected to the
inverting input). A recessive level is read when rx0
> rx1. A dominant level is read when rx1 > rx0.
When the CoBy Bit in the Bus Configuration
Register (2FH) is a 1, input comparison is disabled,
and rx0, which is still connected to the non-inverting
input of the comparator, is the CAN bus line input.
For this configuration, the DcR0 bit of the Bus
Configuration Register must be a 0.
CC
level. No falling edge on the reset_n pin is
CC
remains at a valid level (i.e.,
Description
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CC
March 12, 2009
is driven to a
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