msm80c86a-10js Oki Semiconductor, msm80c86a-10js Datasheet - Page 15

• Manufacturer Part Number: msm80c86a-10js
• Description: 16-bit Cmos Microprocessor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
PIN DESCRIPTION
AD
ADDRESS DATA BUS: Input/Output
A
ADDRESS/STATUS: Output
BHE/S
BUS HIGH ENABLE/STATUS: Output
RD
READ: Output
READY
READY:Input
INTR
INTERRUPT REQUEST: Input
16
These lines are the multiplexed address and data bus.
These are the address bus at the T1 cycle and the data bus at the T2, T3, TW and T4 cycles.
At the T1 cycle, AD
impedance during interrupt acknowledge and hold acknowledge.
These are the four most significant addresses, at the T1 cycle. Accessing I/O port address,
these are low at T1 cycles. These lines are Status lines at T2, T3, TW and T4 cycles. S
are encoded as shown.
These lines are high impedance during hold acknowledge.
This line indicates Data Bus High Enable (BHE) at the T1 cycle. This line is status line at T2,
T3, TW and T4 cycles.
This line indicates that CPU is in the memory or I/O read cycle.
This line is the read strobe signal when CPU read data from memory or I/O device. This line
is active low.
This line is high impedance during hold acknowledge.
This line indicates to the CPU that the addressed memory or I/O device is ready to read or
write.
This line is active high. If the setup and hold time is out of specification, illegal operation will
occur.
This line is the level triggered interrupt request signal which is sampled during the last clock
cycle of instruction and string manipulation.
It can be internally masked by software.
This signal is active high and internally synchronized.
0
/S
- AD
S
0
1
0
1
3
3
. A
7
15
17
/S
S
0
0
1
1
4
4
, A
18
/S
5
Alternate Data
Stack
Code or None
Data
0
, A
low indicates Data Bus Low (D
19
Characteristics
/S
6
0
-D
7
) Enable. These lines are high
MSM80C86A-10RS/GS/JS
3
and S
15/37
4