msm82c54-2rs Oki Semiconductor, msm82c54-2rs Datasheet
msm82c54-2rs
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msm82c54-2rs Summary of contents
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... MSM82C54-2RS/GS/JS CMOS PROGRAMMABLE INTERVAL TIMER GENERAL DESCRIPTION The MSM82C54-2RS/GS/ programmable universal timer designed for use in microcomputer systems. Based on silicon gate CMOS technology, it requires a standby current of only 10 mA (max.) when the chip is in the non-selected state. And during timer operation, the power consumption is still very low with only 10mA (max ...
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... Semiconductor FUNCTIONAL BLOCK DIAGRAM V CC GND Data Counter Bus Buffer 8 Read/ Counter Write Logic Counter Control Word Register Internal Bus MSM82C54-2RS/GS/JS CLK 0 GATE 0 #0 OUT 0 CLK 1 GATE 1 #1 OUT 1 CLK 2 GATE 2 #2 OUT 2 2/23 ...
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... Semiconductor PIN CONFIGURATION (TOP VIEW) 24 pin Plastic DIP 32 pin Plastic SSOP 28 pin Plastic QFJ MSM82C54-2RS/GS/ CLK OUT GATE GND 1 32 ...
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... OH 0 £ V £ 4 5 £ –40°C to +85°C OUT CC –0 ≥ V –0 £ 0 =100 ns MSM82C54-2RS/GS/JS Rating Unit –0 +0.5 CC +0.5 CC –55 to +150 °C 0.7 0.9 Typ. Max. Unit 5 5.5 V +25 +85 °C — +0.8 V — ...
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... ODG 0.8 V and V = 2.2 V for both inputs and outputs MSM82C54-2RS/GS/ –40°C to +85°C) 82C54-2 Conditions Unit Min. Max. 30 — — — ns — — — 184 ...
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... Mode WR CLK GATE PWL OUT Valid Count PWH CLK ODG MSM82C54-2RS/GS/JS Counter Latch 6/23 ...
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... Output of counter output wave form in accordance with the set mode and count value. Adress Bus Control Bus Data Bus 8 bits MSM82C54-2 Counter #0 Counter #1 Counter #2 OUT GATE CLK OUT GATE CLK OUT GATE CLK MSM82C54-2RS/GS/JS Function thru switched to high bits 8 bits 7/23 ...
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... Data Bus to Control Word Register Writing Data Bus from Counter #0 Writing Data Bus from Counter #1 Writing Data Bus from Counter #2 Writing Data Bus in High Impedance Status RL1 RL0 M2 M1 Read/Load Mode (CS=0, A MSM82C54-2RS/GS/ BCD BCD =1, 1, RD=1, WR= 8/23 ...
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... Write the initial count value according to the count value read/write format specified by the control word. Note: Unlike the MSM82C53-2, the MSM82C54-2 allows count value setting for another counter between LSB and MSB settings. MSM82C54-2RS/GS/JS Set Contents Set Contents Set Contents ...
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... The minimum and maximum count values which can be counted in each mode are listed below. Mode MIn. Max Remarks 0 executes 10000H count (ditto in other mdoes) — 1 cannot be counted 1 cannot be counted — — MSM82C54-2RS/GS/JS 10/23 ...
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... Internal Block Diagram of a Counter Control Word Register Control Logic GATE n CLK OUT n n Internal Data Bus Status Latch CR M Status Register NOTE : MSM82C54-2RS/GS/ Count Register MSB M : Count Register LSB L Counter Element : Output Latch MSB M : Output Latch LSB L 11/23 ...
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... When it is set to “H” level again from “L” level, gate retriggering occurs, the CR count value is loaded again, and counting continues. • Count value writing during counting It does not affect the one-shot pulse being counted until retriggering occurs. MSM82C54-2RS/GS/JS 12/23 ...
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... The output is initially set to “H” level. The initial count value is loaded to the CE at the falling edge of the next clock pulse, and is decremented consecutive clock pulses. When the counter value becomes 2, the output is set to “L” level, the initial value is reloaded and then the above operation is repeated. MSM82C54-2RS/GS/JS 13/23 ...
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... N+1 clock pulses are input after triggering. • Gate function: The initial count value is loaded to the CE at the falling edge of the clock pulse succeeding gate triggering. The count sequence can be retriggered. The gate pulse does not affect the output. MSM82C54-2RS/GS/JS 14/23 ...
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... Counting not possible 2 (2) Counter output forced to "H" level (1) Counting not possible 3 (2) Counter output forced to "H" level 4 Counting not possible 5 MSM82C54-2RS/GS/JS Rising Edge "H" Level Counting possible (1) Start of counting (2) Retriggering Start of counting Counting possible Start of counting Counting possible ...
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... Figures in these diagrams refer to counter values. MSM82C54-2RS/GS/ (n= ...
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... MOV MOV ¥ ¥ ¥ ¥ Denotes counter latching Write in control word address (n3) The counter value at this point is latching Reading of the LSB of the counter value latched from counter #1. n1: Conter #1 address Reading of MSB from counter #1 MSM82C54-2RS/GS/JS 17/23 ...
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... RL1 RL0 Output pin status Output pin status Null count Count value reading is effective Programmed mode of counter 5 0 (See the control word format.) MSM82C54-2RS/GS/ and CNT0 ...
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... Result Null count = 1 Null count = 1 Null count = 0 , COUNT and STATUS bits, to 00. This is functionally the 3 Counter 0 Contents Count Status Count Status Count Status (NOTE) MSM82C54-2RS/GS/JS Counter 1 Counter 2 L — — — — L — L — — — — ...
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... MSM82C54-2 used as a 32-bit counter. Use counter #1 and counter #2 Counter #1: mode 0, upper order 16-bit counter value Counter #2: mode 2, lower order 16-bit counter value This setting enables counting maximum of 2 MSM82C54 -2 CLK OUT 0 0 CLK OUT 1 1 CLK OUT 2 2 MSM82C54-2RS/GS/ 20/23 ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM82C54-2RS/GS/JS (Unit : mm) Package material Epoxy resin ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM82C54-2RS/GS/JS (Unit : mm) Package material Epoxy resin ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MSM82C54-2RS/GS/JS (Unit : mm) Package material Epoxy resin ...