74AHC02D,118 NXP Semiconductors, 74AHC02D,118 Datasheet

IC QUAD 2-IN NOR GATE 14SOIC

74AHC02D,118

Manufacturer Part Number
74AHC02D,118
Description
IC QUAD 2-IN NOR GATE 14SOIC
Manufacturer
NXP Semiconductors
Series
74AHCr
Datasheet

Specifications of 74AHC02D,118

Number Of Circuits
4
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Logic Type
NOR Gate
Number Of Inputs
2
Current - Output High, Low
8mA, 8mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Product
NOR
Logic Family
AHC
High Level Output Current
- 8 mA
Low Level Output Current
8 mA
Propagation Delay Time
2.9 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74AHC02D-T
74AHC02D-T
935262692118
1. General description
2. Features
3. Ordering information
Table 1.
Type number
74AHC02
74AHC02D
74AHC02PW
74AHC02BQ
Ordering information
Package
Temperature range Name
40 C to +125 C
40 C to +125 C
40 C to +125 C
The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.
I
I
I
I
I
I
I
74AHC02; 74AHCT02
Quad 2-input NOR gate
Rev. 04 — 21 May 2008
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accept voltages higher than V
Input levels:
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
N
N
N
N
N
For 74AHC02: CMOS level
For 74AHCT02: TTL level
HBM EIA/JESD22-A114E exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101C exceeds 1000 V
SO14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
3
CC
0.85 mm
Product data sheet
Version
SOT108-1
SOT402-1
SOT762-1

Related parts for 74AHC02D,118

74AHC02D,118 Summary of contents

Page 1

Quad 2-input NOR gate Rev. 04 — 21 May 2008 1. General description The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL specified in compliance with JEDEC ...

Page 2

... NXP Semiconductors Table 1. Ordering information Type number Package Temperature range Name 74AHCT02 74AHCT02D +125 C 74AHCT02PW +125 C 74AHCT02BQ +125 C 4. Functional diagram mna216 Fig 1. Logic symbol 74AHC_AHCT02_4 Product data sheet …continued Description SO14 plastic small outline package; 14 leads; body width 3.9 mm TSSOP14 plastic thin shrink small outline package ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning GND Fig 4. Pin configuration SO14 and TSSOP14 5.2 Pin description Table 2. Pin description Symbol Pin GND 74AHC_AHCT02_4 Product data sheet 001aac919 Fig 5. Description data output data input data input data output data input data input ...

Page 4

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage ...

Page 5

... NXP Semiconductors Table 5. Operating conditions Symbol Parameter 74AHCT02 V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). ...

Page 6

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHCT02 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage 8 LOW-level output voltage 8 input leakage GND current 5 supply current 5 additional per input pin; ...

Page 7

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74AHCT02 4 5 propagation nA nY; see pd delay power pF dissipation V = GND capacitance [1] Typical values are measured at nominal supply voltage (V [ the same as t and PLH PHL ...

Page 8

... NXP Semiconductors Test data is given in Table Definitions test circuit termination resistance should be equal to output impedance load capacitance including jig and probe capacitance. L Fig 7. Load circuitry for measuring switching times Table 9. Test data Type Input V I 74AHC02 V CC 74AHCT02 3.0 V 74AHC_AHCT02_4 Product data sheet ...

Page 9

... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 11

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 12

... Document ID Release date 74AHC_AHCT02_4 20080521 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 74AHC_AHCT02_3 20080107 74AHC_AHCT02_2 ...

Page 13

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 14

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 14 Revision history ...

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