ax88783lf ASIX Electronics Corporation, ax88783lf Datasheet - Page 18
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ax88783lf
Manufacturer Part Number
ax88783lf
Description
2-port 10/100m Fast Ethernet Controller
Manufacturer
ASIX Electronics Corporation
Datasheet
1.AX88783LF.pdf
(61 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AX88783LF
Manufacturer:
TEXAS
Quantity:
125
MII0_TX_CLK
MII0_CRS
MII0_COL
MII0_TX_EN
MII0_TXD0
MII0_TXD1
MII0_TXD2
MII0_TXD3
MII0_RX_CLK
MII0_RX_DV
MII0_RXD0
MII0_RXD1
MII0_RXD2
MII0_RXD3
MII0_MDIO
MII0_MDC
Signal Name
2.1.3 Reverse MII Mode
O3/8mA
O3/8mA
O3/8mA
O3/8mA
B3/8mA
I/O
O3
O3
O3
I3
I3
I3
I3
I3
I3
I3
I3
AX88783
Pin No.
100
101
112
113
120
121
122
123
107
108
70
71
91
92
96
97
Port 0 Transmit clock output
Port 0 Carrier Sense. Please connect this signal to MII0_TX_EN
enable signal.
Pull-Down with a 4.7KOhm resistor to ground. (Reverse MII mode
only support full duplex mode)
Port 0 Transmit data valid. MII0_TX_EN is asserted high when valid
data is present on transmit data bus [3:0].
Port 0 Transmit data bit 0 synchronously with respect to the rising
edge of MII0_TX_CLK.
Port 0 Transmit data bit 1 synchronously with respect to the rising
edge of MII0_TX_CLK.
Port 0 Transmit data bit 2 synchronously with respect to the rising
edge of MII0_TX_CLK.
Port 0 Transmit data bit 3 synchronously with respect to the rising
edge of MII0_TX_CLK.
Port 0 Transmit clock output
Port 0 Receive data enable. MII0_RX_DV is asserted high to indicate
a valid receive data bus [3:0]
Port 0 Receive data bit 0 synchronously with respect to the rising edge
of MII0_RX_CLK.
Port 0 Receive data bit 1 synchronously with respect to the rising edge
of MII0_RX_CLK.
Port 0 Receive data bit 2 synchronously with respect to the rising edge
of MII0_RX_CLK.
Port 0 Receive data bit 3 synchronously with respect to the rising edge
of MII0_RX_CLK.
Note: Pull-Down with a 4.7K ohm resistor to ground
MII management Data. Serial data input/output transferred from/to the
external connected MAC device. The transfer protocol should
conform to the IEEE 802.3u MII spec.
MII management clock input from the externally connected Ethernet
MAC device. All data transferred on MII0_MDIO are synchronized to
the rising edge of this clock.
Note: P0SMR0 Slave MDIO Register need to be programmed.
18
2-Port 10/100M Fast Ethernet Controller
Description
ASIX ELECTRONICS CORPORATION
Non-PCI 8/16/32-Bit
AX88782/AX88783