ax88783lf ASIX Electronics Corporation, ax88783lf Datasheet - Page 4
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ax88783lf
Manufacturer Part Number
ax88783lf
Description
2-port 10/100m Fast Ethernet Controller
Manufacturer
ASIX Electronics Corporation
Datasheet
1.AX88783LF.pdf
(61 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AX88783LF
Manufacturer:
TEXAS
Quantity:
125
4.0
5.0
3.20
3.21
4.1
4.2
4.3
4.4
5.1
4.1.1
4.2.1
4.3.1
4.3.2
4.3.3
4.3.4
4.4.1
4.4.2
4.4.3
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
5.1.10
5.1.11
5.1.12
5.1.13
5.1.14
5.1.15
5.1.16
5.1.17
INTERFACE ......................................................................................................................................................31
INTERNAL REGISTER CONFIGURATION ...............................................................................................32
5.1.9.1
5.1.9.2
5.1.9.3
5.1.16.1
5.1.16.2
5.1.16.3
5.1.16.4
5.1.16.5
5.1.16.6
5.1.16.7
5.1.16.8
5.1.17.1
5.1.17.2
5.1.17.3
5.1.17.4
5.1.17.5
5.1.17.6
5.1.17.7
5.1.17.8
5.1.17.9
5.1.17.10
5.1.17.11
5.1.17.12
GPIO I
CPU I
MII I
R
RMII
CPU R
MAC R
EVERSE
MII Interface Set-Up Procedure ...............................................................................................................31
Reverse MII Interface Set-Up Procedure .................................................................................................31
RMII Mode Reference connection ...........................................................................................................31
RMII Interface Set-Up Procedure ............................................................................................................31
Reverse RMII Mode Reference connection: (Only support 100 Full Duplex mode)...............................31
Reverse RMII Interface Set-Up Procedure...............................................................................................31
8-Bit CPU Burst Read/Write Operation ...................................................................................................31
16-Bit CPU Burst Read/Write Operation .................................................................................................31
32-Bit CPU Burst Read/Write Operation .................................................................................................31
Chip revision ID and Reset Register (CIRR) ...........................................................................................32
PHY0 /PHY1 Configuration Register (PCR) ...........................................................................................32
PHY0/PHY1 Status Register (PSR) .........................................................................................................32
Global MAC Configuration Register (GMCR) ........................................................................................32
Layer 2 Global Configuration Register (LGCR)......................................................................................32
Layer 2 Learning/Aging/OneSA Control Register (LLCR) .....................................................................32
Layer 2 Routing Table Entry Read/Write Register (LRCR0 and LRCR1) ..............................................32
802.1D and Port-based VLAN Configuration Register (PVCR) .............................................................32
Sniffer Function Configuration Register (SFCR0, SFCR1, SFCR2) ......................................................32
QoS Priority Mapping Table Register (QPTR) ........................................................................................32
802.1Q-in-1Q (Double-Tagging) Configuration Register (QCR)............................................................32
Port Pair and MDC Control Register (PPMR) .........................................................................................32
MDIO Read/Write Control Register (MRCR) .........................................................................................32
TCP/IP Offload Control Register (TOCR)...............................................................................................32
CPIO Control Register ( CCR )................................................................................................................32
Security Mac Control Registers................................................................................................................32
VLAN Entry Registers .............................................................................................................................33
NTERFACE
AND
NTERFACE
EAD
NTERFACE
Sniffer Function Configuration Register 0 (SFCR0)............................................................................................. 32
Sniffer Function Configuration Register 1 (SFCR1)............................................................................................. 32
Sniffer Function Configuration Register 2 (SFCR2)............................................................................................. 32
EGISTER
MII I
Security Mac 0 Control Register (SM0CR0, SM0CMR1)................................................................................ 32
Security Mac 1 Control Register (SM1CR0, SM1CR1) ................................................................................... 32
Security Mac 2 Control Register (SM2CR0, SM2CR1) .................................................................................. 32
Security Mac 3 Control Register (SM3CR0, SM3CR1) ................................................................................... 32
Security Mac 4 Control Register (SM4CR0, SM4CR1) .................................................................................. 32
Security Mac 5 Control Register (SM5CR0, SM5CR1) ................................................................................... 33
Security Mac 6 Control Register (SM6CR0, SM6CR1) ................................................................................. 33
Security Mac 7 Control Register (SM7CR0, SM7CR1) ................................................................................. 33
VLAN Entry 0 Register (VER0)....................................................................................................................... 33
VLAN Entry 1 Register (VER1)....................................................................................................................... 33
VLAN Entry 2 Register (VER2)....................................................................................................................... 33
VLAN Entry 3 Register (VER3)....................................................................................................................... 33
VLAN Entry 4 Register (VER4)....................................................................................................................... 33
VLAN Entry 5 Register (VER5)....................................................................................................................... 33
VLAN Entry 6 Register (VER6)....................................................................................................................... 33
VLAN Entry 7 Register (VER7)....................................................................................................................... 33
VLAN Entry 8 Register (VER8)....................................................................................................................... 33
VLAN Entry 9 Register (VER9)....................................................................................................................... 33
VLAN Entry 10 Register (VER10)................................................................................................................... 33
VLAN Entry 11 Register (VER11)................................................................................................................... 33
R
/W
EVERSE
RITE
NTERFACE
.................................................................................................................................................31
D
P
S
ROTOCOL
EFINITION
O
UPPORT
RMII I
PERATION
(O
(O
NTERFACE
.............................................................................................................................31
NLY
.............................................................................................................................32
NLY FOR
.........................................................................................................................31
S
UPPORT
.............................................................................................................31
AX88783) ..........................................................................................31
100M F
4
ULL
D
UPLEX
2-Port 10/100M Fast Ethernet Controller
M
ASIX ELECTRONICS CORPORATION
ODE
) .........................................................31
Non-PCI 8/16/32-Bit
AX88782/AX88783