ch7028b Chrontel, ch7028b Datasheet

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... Rev. 1.1, 08/21/2008 CH7028B Advance Information General Description The CH7028B is a device targeting handheld and similar systems which accept digital input signal, and encodes and transmits data through 10-bit DACs. The device is able to encode the video signals and generate synchronization signals for NTSC and PAL standards. The device accepts different data formats including RGB and YCbCr (e ...

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... PLL XO SYNC H,V,DE position adjust 2 SDRAM CSC (YCbCr Scaler MUX (RGB to to RGB) MUX BRI CON VP HP Composite sync generation Figure 1: CH7028B Block Diagram 209-1000-001 CH7028B HUE SAT CSC BRI TV CON formater YUV CVBS/Y-Svideo DAC 0 CVBS/C-Svideo DAC 1 Rev. 1.1, 08/21/2008 ...

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... TV Connection Detect .........................................................................................................................14 2.2.5 Picture Enhancement............................................................................................................................14 2.2.6 Color Sub-Carrier Generation ..............................................................................................................15 2.2.7 ITU-R BT.470 Compliance..................................................................................................................15 2.2.8 SDRAM Power Down .........................................................................................................................15 2.2.9 Test Pattern Select................................................................................................................................15 3.0 Electrical Specifications ...................................................................................................................................16 3.1 Absolute Maximum Ratings .....................................................................................................................16 3.2 Recommended Operating Conditions .......................................................................................................16 3.3 Electrical Characteristics ..........................................................................................................................17 3.4 Digital Inputs / Outputs.............................................................................................................................17 3.5 AC Specifications .....................................................................................................................................18 4.0 Package Dimensions.........................................................................................................................................19 5.0 Revision History ...............................................................................................................................................21 209-1000-001 Rev. 1.1, 08/21/2008 Table of Contents CH7028B 3 ...

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... Figure 9: 64 Pin LQFP Package .......................................................................................................................................20 LIST OF TABLES Table 1: Pin Name Description (BGA Package) ................................................................................................................7 Table 2: Pin Name Descriptions (LQFP64 Package)..........................................................................................................9 Table 3: Input Data Format...............................................................................................................................................13 Table 4: Supported SDTV Standards................................................................................................................................14 Table 5: Video DAC Configurations for CH7028B .........................................................................................................14 Table 6: Test Pattern Selection .........................................................................................................................................15 4 Figures and Tables 209-1000-001 CH7028B Rev ...

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... CHRONTEL 1.0 Pin-out 1.1 Package Diagram Figure 2: 80 pin BGA Package(Top view) 209-1000-001 Rev. 1.1, 08/21/2008 CH7028B ...

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... CHRONTEL ATPG ResetB 5 AGND 6 AVDD 7 GNDQ_MEM 8 VDDQ_MEM 9 AGND 10 AVDD 11 GND_MEM 12 VDD_MEM 13 VDDQ_MEM 14 GNDQ_MEM CH7028B Figure 3: 64 pin LQFP Package 209-1000-001 CH7028B D[7] 48 D[ D[4] D[3] 44 D[2] 43 D[ VDDIO 39 GCLK AVDD 38 37 AGND 36 GND_MEM 35 GND_MEM 34 VDD_MEM 33 NC Rev. 1.1, 08/21/2008 ...

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... CVBS, S-video, YPbPr or Analog RGB output Full swing 1.3 V. CVBS, S-video, YPbPr or Analog RGB output Full swing 1.3 V. Current Set This pin sets the DAC current. A 1.2k Ω, 1% tolerance resistor should be connected between this pin and AGND_DAC using short and wide trace. CH7028B 7 ...

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... DAC power supply (2.5 – 3.3V) SDRAM output buffer supply voltage (2.5V) SDRAM device supply voltage (2.5V) Digital supply ground Analog supply ground PLL supply ground DAC supply ground SDRAM output buffer supply ground SDRAM device supply ground All the NC pins should be left open. 209-1000-001 Rev. 1.1, CH7028B 08/21/2008 ...

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... For some situation of the slave mode, a parallel resonance crystal (± 20 ppm) should be attached between this pin and XO. external 3.3V CMOS compatible clock can drive the XI/FIN input. Crystal Output For some situation of the slave mode, a parallel resonance crystal (± 20 CH7028B Ω tolerance resistor should However ...

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... Analog supply voltage (2.5-3.3V). PLL supply voltage (1.8V). DAC power supply (2.5-3.3V). SDRAM output buffer supply voltage (2.5V). SDRAM device supply voltage (2.5V). Digital supply ground. Analog supply ground. PLL supply ground. DAC supply ground. SDRAM output buffer supply ground. SDRAM device supply ground. 209-1000-001 CH7028B Rev. 1.1, 08/21/2008 ...

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... CH7028B is latched with one edge of the clock (also known as single edge transfer mode or SDR). For the unitary data, clock at 1X pixel rate, the data applied to the CH7028B is latched with one edge of the clock. The polarity of the pixel clock can be reversed under serial port control. Hsync and Vsync can be input individually or embedded into data signal such as BT656 input format ...

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... The VREF value can be 80%, 70%, 60% and 50% of VDDIO value, referring to VRTM[1:0]. The pseudo differential mode can accept the wide range of the input voltage level from 1.2v to 3.3v, while the CMOS mode can accept 1.8v to 3.3v input voltage. 2.1.4 Input Data Format The following table indicates the supported input data format by CH7028B Figure 6: Vertical Input Timing … ...

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... (PA,PB,PC represent the parts of one pixel data) IDF[3:0] describes the major input data format that CH7028B accepts. They are: (Table 10) IDF = 0: Multiplexed 888 RGB input IDF = 1: Multiplexed 666 RGB input IDF = 2: Multiplexed 565 RGB input IDF = 3: Multiplexed 555 RGB input ...

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... The DAC output of CH7028B can be single terminated or double terminated. Using single termination will save power consumption while double termination is likely to minimize the reflection from the cable. Refer to the description of register bit SEL_R. 2.2.4 TV Connection Detect CH7028B can detect the TV connection by setting register SPPSNS. It can detect which DAC is connected, short to ground or not connected. 2.2.5 Picture Enhancement 14 ...

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... SDRAM parts support either power down or deep power down mode. In these cases, even CH7028B enters into power down, the current consumption is still large ( > 100μA ). This current is primarily derived from the SDRAM die. ...

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... Memory core supply VDD18 Generic for all 1.8V supplies VDD33 Generic for all 3.3V supplies Ambient operating temperature 16 Min Typ [1] -0.5 [2] -0.5 [3] GND – 0.5 -40 -40 Min 2.5 2.5 1.71 1.71 1.14 2.375 2.375 1.71 2.5 -20 209-1000-001 CH7028B Max Units 2.5 V 5.0 VDDIO+0.5 V °C 85 °C 150 °C 150 260 °C 245 225 Typ Max Units 3.3 3.5 V 3.3 3.5 V 1.8 1. ...

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... Applies to HSO, VSO, CSYNC. 209-1000-001 Rev. 1.1, 08/21/2008 Min 10 [1] [2] Test Condition Min I = 3.0 mA GND-0.5 OL 1.0 GND-0.5 0.25 VDDIO/2 +0.25 GND-0.5 VDD33 – 0.5 GND-0.5 VDD33 VDD33 0.1 IN CH7028B Typ Max Units 10 10 bits 0 μA <20 Typ Max Unit 0.4 V VDD33 + V 0.5 0 VDDIO + V 0 ...

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... S V and DE to GCLK Hold Time: D[17:0 and DE to GCLK t De-skew time increment STEP 18 Test Condition Min Typ 2.3 1 < 1.2ns GCLK to D[17:0], 0. Vref D[17:0 0.5 = Vref to GCLK 50 209-1000-001 CH7028B Max Unit 64 MHz 120 MHz Rev. 1.1, 08/21/2008 ...

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... Max Notes: All dimensions conform to JEDEC standard MO-216. 209-1000-001 Rev. 1.1, 08/21/2008 Figure 8: 80 Pin BGA Package SYMBOL 5.00 0.50 4.00 0.50 1.20 CH7028B A1 Conrer Bottom View ) ...

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... Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. 3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side Figure 9: 64 Pin LQFP Package SYMBOL 0.17 1.35 0.05 0.50 0.27 1.45 0.15 209-1000-001 CH7028B LEAD CO-PLANARITY E .004 “ 0.45 0.09 0° 1.00 0.75 0.20 7° Rev. 1.1, 08/21/2008 ...

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... CHRONTEL 5.0 Revision History Rev. # Date Section 1.0 11/04/2007 All 1.1 08/21/2008 2.1 209-1000-001 Rev. 1.1, 08/21/2008 Description Initial preliminary release. Add input timing figure. Add BGA package. CH7028B 21 ...

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... LQFP, Lead-free, CH7028B-TF-TR Tape & reel CH7028B-TFI 64 LQFP, Lead-free 64 LQFP, Lead-free, CH7028B-TFI-TR Tape & reel CH7028B-GF 80BGA, Lead-free 80BGA, Lead-free, CH7028B-GF-TR Tape & reel Chrontel International Limited ©2008 Chrontel - All Rights Reserved. 22 Disclaimer ORDERING INFORMATION Copy Operating Temperature Range Protection None Commercial : -20 to 70° ...