ch7028b Chrontel, ch7028b Datasheet - Page 15

• Manufacturer Part Number: ch7028b
• Description: Chrontel Ch7028b Sdtv Encoder
• Manufacturer: Chrontel

CHRONTEL
The CH7028B has the capability of vertical and horizontal output picture position adjustment. It can automatically put
the picture in the display center, and the vertical or horizontal position is also programmable through user input. And
also it can provide brightness, contrast, hue, saturation adjustment and text enhancement functions.
CH7028B also supports vertical or horizontal flip and rotation (0, 90, 180 and 270 degree) functions.
2.2.6 Color Sub-Carrier Generation
CH7028B has two ways to generate the color sub-carrier frequency. If the GCLK from the graphics controller has a
steady center frequency and very small jitters, the sub-carrier can be derived from the GCLK. However, since even a
±0.01% sub-carrier frequency variation is enough to cause some TV to lose color lock, CH7028B has the ability to
generate the sub-carrier frequency from the crystal when the GCLK from the graphics device cannot meet the
requirement. In this case, the crystal has to be present.
In addition, CH7028B has the capability to gen-lock the color sub-carrier with Vsync. Also, it has the ability to operate
in a “stop dot crawl” mode for NTSC CVBS output when the first sub-carrier generation method is used.
2.2.7 ITU-R BT.470 Compliance
The CH7028B is mostly compliant with ITU-R BT.470 standard except for the items below.
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2.2.8 SDRAM Power Down
SDRAM have two kinds of power down modes. One is power down mode, the other is deep power down mode. For
power down mode, all data contents will be held in the bank. For deep power down mode, a command is required to
issued. There is a bit called MEMPD in register map. It can be used to enable the deep power mode. During deep power
mode, all the data in memory banks will be lost, and the SDRAM leakage current is less than 1μA. A very important
thing required to be noted here is that not all the SDRAM parts support either power down or deep power down
mode. In these cases, even CH7028B enters into power down, the current consumption is still large ( > 100μA ). This
current is primarily derived from the SDRAM die.
2.2.9 Test Pattern Select
Setting TSTP[3:0] bit[3:0] of 04h on the second page of register map( refer to PG register bit0 of 03h on the first page)
can select different video patterns that go through datapath, according to the following table. TEST(bit5 of 04h on the
second page) is the test pattern selection enable. It has to be 1 to enable test mode. TSYNC(bit4 of 04h on the second
page) is to select which sync will be used internally generated sync or external input sync.
209-1000-001
The frequencies of horizontal sync, vertical sync, and color sub-carrier depend on the quality of GCLK from
graphics controller and/or the off-chip crystal.
It is assumed that gamma correction, if required, is performed in the graphics device.
Pulse widths and rise/fall times for sync pulses, front/back porches, and equalizing pulses are designed to
approximate ITU-R BT.470 requirements. However, they may have a small variation depending on the actual input
and output format.
The actual bandwidths of the luminance and chrominance signals depend on the input resolution and the filter
selection.
Rev. 1.1,
Table 6: Test Pattern Selection
TSTP[3:0]
0
1
2
3
4
5
6
08/21/2008
One pixel wide color bar
Horizontal ramp
Vertical ramp
Test pattern
Color bar
Zigzag
White
Black
CH7028B
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