ch7021a-tef-tr Chrontel, ch7021a-tef-tr Datasheet
ch7021a-tef-tr
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ch7021a-tef-tr Summary of contents
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... Chrontel CH7021/CH7022 SDTV / HDTV Encoder Features • VGA to SDTV/EDTV/HDTV conversion supporting graphics resolutions up to 1600x1200 • HDTV support for 480p, 576p, 720p, 1080i and 1080p • Support for NTSC, PAL, SECAM color modulation. TM • 7.1.L1 copy protection support for Macrovision SDTV (CH7021 only) TM • ...
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... CHRONTEL XI/FIN,XO 2 TVCLK(+,-) BCO/VSYNC C/HSYNC D1,D2,D3 Clock Color Space SDVO_Clk(+,-) Driver Conversion 2 10bit-8bit decoder SDVO_R(+,-) Data Latch, SDVO_G(+,-) Serial to Parallel 6 SDVO_B(+,-) 2 Serial Port PLL Control Control 3 CVBS, S-Video, NTSC/PAL/ RGB, YPbPr SECAM Encoder Scaling Scan Conv Flicker Filt HDTV YPbPr Encoder RGB, Bypass ...
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... CHRONTEL 1.0 Pin-Out ____________________________________________________________________ 5 1.1 Package Diagram ___________________________________________________________________5 1.2 Pin Description _____________________________________________________________________7 2.0 Functional Description_______________________________________________________ 10 2.1 Input Interface_____________________________________________________________________10 2.2 TV Output Operation _______________________________________________________________10 2.3 CRT Bypass Operation ______________________________________________________________13 2.4 Command Interface ________________________________________________________________13 2.5 D-Connector ______________________________________________________________________14 2.6 Boundary scan Test_________________________________________________________________14 3.0 Register Control ____________________________________________________________ 16 4.0 Electrical Specifications ______________________________________________________ 17 4.1 Absolute Maximum Ratings __________________________________________________________17 4.2 Recommended Operating Conditions ___________________________________________________17 4 ...
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... CHRONTEL List of Figures Figure 1: Functional Block Diagram .............................................................................................................................2 Figure 2: 64-Pin LQFP Package ....................................................................................................................................5 Figure 3: 64-Pin QFN Package......................................................................................................................................6 Figure 4: Control Bus Switch ......................................................................................................................................13 Figure 5: NAND Tree Connection...............................................................................................................................14 Figure 6: 64 Pin LQFP (Exposed Pad) Package ..........................................................................................................23 Figure 7: 64 Pin QFN Package ( 0.8mm) .........................................................................................................24 List of Tables Table 1: Pin Description ................................................................................................................................................7 Table 2: CH7021/CH7022 supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns ...
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... SD_DDC 2 3 SC_DDC 4 SD_PROM 5 SC_PROM 6 DVDD 7 RESET DGND 10 DGND 11 SPD 12 SPC 13 DVDD 14 BSCAN VDAC2 201-0000-065 Rev. 2.1, 4/21/2008 Chrontel CH7021/CH7022 Figure 2: 64-Pin LQFP Package CH7021/CH7022 48 DL3 47 DL2 46 DL1 45 AGND_TVPLL2 44 TVCLK- 43 TVCLK+ 42 AVDD_TVPLL2 41 AVDD_TVPLL1 XI/FIN 38 AGND_TVPLL1 37 DGND 36 VSYNC 35 DVDD 34 CHSYNC ...
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... SD_DDC 2 SC_DDC 3 SD_PROM 4 5 SC_PROM 6 DVDD RESET DGND 10 DGND 11 SPD 12 SPC 13 DVDD 14 BSCAN VDAC2 6 Chrontel CH7021/CH7022 Figure 3: 64-Pin QFN Package 201-0000-065 CH7021/CH7022 48 DL3 47 DL2 46 DL1 45 AGND_TVPLL2 44 TVCLK- 43 TVCLK+ AVDD_TVPLL2 42 41 AVDD_TVPLL1 40 XO XI/FIN 39 38 AGND_TVPLL1 DGND 37 VSYNC 36 DVDD ...
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... CHRONTEL 1.2 Pin Description Table 1: Pin Description Pin # Type Symbol 1,51 Out T1,T2 2 In/Out SD_DDC 3 In/Out SC_DDC 4 In/Out SD_PROM 5 Out SC_PROM 7 In RESET In/Out SPD 12 In/Out SPC 14 In BSCAN 18,20,24,28 Out DACA[3:0] 21,25,29 Out DACB[2:0] ◊ Intel Proprietary. 201-0000-065 Rev. 2.1, 4/21/2008 Description Test These pins are reserved for factory test and default to high impedance ...
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... CHRONTEL Table 1: Pin Description (contd.) Pin # Type Symbol 22,26,30 Out DACC[2: ISET 34 Out CHSYNC 36 Out VSYNC 39 In XI/FIN 40 Out XO 43,44 Out TVCLK+/- 46 Out DL1 47 Out DL2 48 Out DL3 50 In RPLL 53,54,56,57 In SDVO_R+/-, 59,60 SDVO_G+/-, SDVO_B+/- 62,63 In SDVO_CLK+/- 8 Description DAC Output C Video Digital-to-Analog outputs. Refer to section 2.2.2 for information regarding supports for Composite Video, S-Video, SCART, YPrPb and RGB Bypass outputs ...
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... CHRONTEL Table 1: Pin Description (contd.) Pin # Type Symbol 6,13,35 Power DVDD 9,10,37 Power DGND 16 Power VDAC2 17 Power GDAC2 19 Power VDAC1 23 Power GDAC1 27 Power VDAC0 31 Power GDAC0 41 Power AVDD_TVPLL1 38 Power AGND_TVPLL1 42 Power AVDD_TVPLL2 45 Power AGND_TVPLL2 52,58,64 Power AVDD 49,55,61 Power AGND 33 Power V5V 201-0000-065 Rev. 2.1, 4/21/2008 Description (2 ...
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... CHRONTEL 2.0 Functional Description 2.1 Input Interface 2.1.1 Overview One pair of differential clock signal and three differential pairs of data signals (R/G/B) form one channel data. The input data are 10-bit serialized data. Input data run at 1Gbits/s~2Gbits/s, being a 10x multiple of the clock rate (SDVO_CLK+/-). The CH7021/CH7022 de-serializes the input into 10-bit parallel data with synchronization and alignment ...
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... CHRONTEL Table 3: Various VGA resolutions. Name Resolution 320x200 QVGA 320x240 400x300 640x350, 640x400 VGA 640x480 512x384 704x480, 704x576 720x350, 720x400, 720x480, 720x540, 720x576 768x480, 768x576 SVGA 800x600 832x624 848x480 920x766 960x600 1024x600 XGA 1024x768 1124x768 1152x720 1280x768, 1280x720, 1280x960 SXGA 1280x1024 ...
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... CHRONTEL Table 5: Supported EDTV/HDTV standards Standards Field/Frame Rate(Hz) 480/60p SMPTE293M 60/1.001 EIA770.2A 576/50p ITU-R BT1358 50 720/60p SMPTE296M 60 or 60/1.001 720/50p SMPTE296M 50 1080/60i SMPTE274M 60 or 60/1.001 1080/50i SMPTE274M 50 1080/50i SMPTE295M 50 1080/30p SMPTE274M 30 or 30/1.001 1080/25p SMPTE274M 25 1080/24p SMPTE274M 24 or 24/1.001 1080/60p SMPTE274M 60 or 60/1 ...
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... CHRONTEL feature is important since even a ±0.01% subcarrier frequency variation is enough to cause some televisions to lose color lock. 2.2.6 TV picture adjustment The CH7021/CH7022 has the capability of vertical and horizontal output picture position adjustment. The CH7021/CH7022 will automatically put the picture in the display center, and the position is also programmable through user input ...
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... CHRONTEL redirection circuitry to the appropriate destination (ADD2 PROM or DDC). Redirecting the traffic to internal registers while at the stage of traffic to DDC occurs on observing a STOP after a START on the control bus. 2.5 D-Connector The CH7021/CH7022 provides 3 pins ( DL[3: identify the video scanning format and aspect ratio of the output signal from the encoder for digital broadcasting ...
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... CHRONTEL Table 8: Signal Order in the NAND Tree Testing Order Pin Name 1 SD_DDC 2 SC_DDC 3 SD_PROM 4 SC_ PROM 5 RESETB SPD 8 SPC 9 DACA[3] 10 DACA[2] 11 DACB[2] 12 DACC[2] 13 DACA[1] 14 DACB[1] 15 DACC[1] 16 DACA[0] 17 DACB[0] 18 DACC[0] 19 ISET 20 CHSYNC 21 VSYNC 22 XI/FIN TVCLK+ 25 TVCLK- 26 DL1 27 DL2 28 DL3 29 T2 ...
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... CHRONTEL 3.0 Register Control The CH7021/CH7022 is controlled via a serial control port. The serial bus uses only the SC clock to latch data into registers, and does not use any internally generated clocks so that the device can be written to in all power down modes. The device will retain all register values during power down modes. ...
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... CHRONTEL 4.0 Electrical Specifications 4.1 Absolute Maximum Ratings Symbol Description All 2.5V power supplies relative to GND All 3.3V power supplies relative to GND T Analog output short circuit duration SC T Ambient operating temperature AMB T Storage temperature STOR T Junction temperature J Vapor phase soldering (5 second) T VPS Vapor phase soldering (11 second) ...
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... CHRONTEL 4.3 Electrical Characteristics = 0°C – 70°C, VDD25 =2.5V ± 5%, VDD33 = 3. 3V ± 5%,) (Operating Conditions Symbol Description Video D/A Resolution Full scale output current Video level error I Total VDD25 supply current (2.5V supplies) with CVBS VDD25,CVBS output and 1024x768 input I Total VDD25 supply current (2.5V supplies) with S-Video ...
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... CHRONTEL 4.4 DC Specifications Symbol Description SDVO Receiver Differential V RX-DIFFp-p Input Peak to Peak Voltage Z SDVO Receiver DC Differential RX-DIFF-DC Input Impedance Z SDVO Receiver DC Common RX-COM-DC Mode Input Impedance SDVO Receiver Initial DC Z RX-COM-INITIAL- Common Mode Input DC Impedance Z SDVO Receiver Powered RX-COM-High- Down DC Common Mode ...
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... CHRONTEL Symbol Description 6 V RESET* MISC1IL Input Low Voltage 7 AS, BSCAN MISC2IH Input High Voltage 7 V AS, BSCAN, T3 MISC2IL Input Low Voltage I AS, RESET* PU Pull Up Current I BSCAN Pull Down Current 8 V CHSYNC, VSYNC SYNCOH Output High Voltage 8 V CHSYNC, VSYNC ...
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... CHRONTEL 4.5 AC Specifications Symbol Description UI SDVO Receiver Unit Interval for DATA Data Channels f SDVO CLK Input Frequency SDVO_CLK f SDVO Receiver Pixel PIXEL frequency f SDVO Receiver Symbol SYMBOL frequency t SDVO Receiver Minimum Eye RX-EYE Width t SDVO Receiver Max. time RX-EYE-JITTER between jitter median and max. ...
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... CHRONTEL Notes: 1. Refers to the figure below, the delay refers to the time pass through the internal switches. To DDC pin 22 3.3V typ. 2.5V typ. R=5K 201-0000-065 CH7021/CH7022 To SPC/SPD pin Rev. 2.1, 4/21/2008 ...
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... CHRONTEL 5.0 Package Dimensions TOP VIEW Figure 6: 64 Pin LQFP (Exposed Pad) Package Table of Dimensions No. of Leads Milli- MIN 12 10 meters MAX Notes: 1. Conforms to JEDEC standard JESD-30 MS-026D. 2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. ...
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... CHRONTEL TOP VIEW Figure 7: 64 Pin QFN Package ( 0.8mm) Table of Dimensions No. of Leads mm Milli- MIN 6.1 8 meters MAX 6.3 Notes: 1. Conforms to JEDEC standard JESD-30 MO-220. 24 BOTTOM VIEW Pin C SYMBOL ...
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... CHRONTEL 6.0 Revision History Table 10: Revisions Rev. # Date Section 1.0 3/21/05 All 1.1 4/28/05 4.3 4/28/05 4.4 1.2 9/14/05 Figure 1 9/14/05 4.2 9/14/05 1.2 10/12/05 4.4, 4.5 1.22 4/6/07 4.3 1.3 10/3/07 1.1, 5.0 1.31 10/26/07 4.4 2.0 3/21/08 All 2.1 4/21/08 Ordering Information 201-0000-065 Rev. 2.1, 4/21/2008 CH7021/CH7022 Description First official release. Updated symbol names and descriptions Changed DL limits OM Added video switch Added Rset specification Added “10k resistor” to descriptions of pin ...
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... SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Part Number CH7021A-TEF CH7021A-TEF-TR CH7021A-BF CH7021A-BF-TR CH7022A-TEF CH7022A-TEF-TR ...