ch7019 Chrontel, ch7019 Datasheet - Page 12

• Manufacturer Part Number: ch7019
• Description: Ch7019 Tv Encoder / Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
2.2.2
The two 12-bit input data ports, D1[11:0] and D2[11:0], can be grouped together to form a single 24-bit interface to the
graphic controller. In this case the timing signals H1, V1, DE1, XCLK1 and XCLK1* are equal to H2, V2, DE2,
XCLK2 and XCLK2* , respectively. The CH7019 supports 5 different 24-bit data formats. Each of which is used with a
1X pixel rate clock latching data with one of the clock edges (default is falling edge). The 24-bit input data formats are
IDFx[3:0]=5,6,7,8 and 9 (note that IDF1 must be set equal to IDF2) and are illustrated in Figure 8 below.
IDFx
5
6
7
8
9
The pixel data bus represents a 24-bit or 16-bit data stream containing either RGB or YCrCb formatted data. When the
input is a 16-bit YCrCb data stream the color-difference data will be transmitted at half the data rate of the luminance
data, with the sequence being set as Cb0, Y0 transmitted during one clock cycle, followed by Cr0, Y1 the following
clock cycle, where Cb0, Y0, Cr0 refers to co-sited luminance and color-difference samples and the Y1 data refers to the
next luminance sample, per CCIR-601 sampling. Non-active data must be 0 in RGB format, and 16 for Y, 128 for Cr
and Cb in YCrCb formats.
12
Table 6: Multiplexed Input Data Formats (IDFx = 4) with Embedded Sync
IDFx =
Format =
Pixel #
Bus Data
In this mode, the S[7..0] byte contains the following data:
S[6] = F = 1 during field 2, 0 during field 1
S[5] = V = 1 during field blanking, 0 elsewhere
S[4] = H = 1 during EAV (synchronization reference at the end of active video)
S[7] and S[3:0] are ignored
Description
RGB 8-8-8 (1x24-bit) for TV/Bypass RGB
YCrCb 8-8 (1x16-bit with CrCb multiplexed and decimated by 2) for TV
YCrCb 8-8-8 (1x24-bit) for TV
RGB 8-8-8 (2x24-bit) Odd / Even Ganged for LVDS
RGB 8-8-8 (1x24-bit) Normal Ganged for LVDS
Hx
XCLKx
DEx
Dx[11:0]
24-Bit Data Formats
Dx[7]
Dx[6]
Dx[5]
Dx[4]
Dx[3]
Dx[2]
Dx[1]
Dx[0]
0 during SAV (synchronization reference at the start of active video)
Figure 8: Non-Multiplexed Input Data Formats (IDFx = 5,6,7,8 and 9)
P0a
1
1
1
1
1
1
1
1
P0b
0
0
0
0
0
0
0
0
SAV
P1a
0
0
0
0
0
0
0
0
YCrCb 4:2:2 (2x8-bit) for TV
P0
P1b
S[7]
S[6]
S[5]
S[4]
S[3]
S[2]
S[1]
S[0]
P1
4
P2a
Cb2[7]
Cb2[6]
Cb2[5]
Cb2[4]
Cb2[3]
Cb2[2]
Cb2[1]
Cb2[0]
P2
201-0000-048
P3
P2b
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
P4
P3a
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]
Rev. 2.4, 12/18/2006
P5
CH7019B
P3b
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]