kac-9617 ETC-unknow, kac-9617 Datasheet - Page 16

• Manufacturer Part Number: kac-9617
• Description: Kodak Kac-9617 Cmos Image Sensor
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Functional Description
5.3
The KAC-9617 contains a clock generation module (figure 19)
that will create three clocks as follows:
www.kodak.com/go/imagers 585-722-4385
Hclk,
pclk
Aclk
Clock Generation
mclk
Figure 19. Clock Generation Module
the horizontal clock. This is an internal system
clock and can be programmed to be the input
clock (mclk) or mclk divided by any number
between 1 and 31. All exposure times are in
multiples of this clock.
To set the frequency of this clock the HclkGen
bits in the VCLKGEN register should be pro-
gramed.For the new frequency to take effect the
UpdateSettings bit in the UPDATE register
should be set. The timing and control circuit will
set the new Hclk frequency at beginning of the
next frame and reset the UpdateSettings bit in
the UPDATE register.
the pixel clock. This is the external pixel clock
that appears at the digital video port. pclk is
always equal to Hclk except when the sensor is
programmed to work sub-sampling mode in
which case pclk will be equal to Hclk divided by
2. This clock cannot be programed.
the array clock. This is an internal clock used by
the pixel array.Its frequency does not effect the
exposure time.
To set the frequency of this clock the AclkGen
bits in the VCLKGEN register should be pro-
gramed. For the new frequency to take effect the
UpdateSettings bit in the UPDATE register
should be set. The timing and control circuit will
set the new Hclk frequency at beginning of the
next frame and reset the UpdateSettings bit in
the UPDATE register.
÷
÷
÷
HclkGen
ArrayMode
AclkGen
(continued)
Hclk
pclk
Aclk
16
5.4
Full frame integration is when each pixel in the array integrates
light incident on it for the duration of a frame (see Figure 20).
The number of Hclk clock cycles required to process & shift out
one row of pixels is given by:
Where:
The number of rows in a scan window is given by:
Where:
The number of Hclk clocks required to process a full frame is
given by:
Where:
R
R
RAD
RAD
M
SWN
F
The frame rate is given by:
delay
opcycle
delay
factor
FN
Full Frame Integration
end
start
Hclk
rows
= [(M
SWN
is a fixed integer value of 780 representing the
Row Operation Cycle Time in multiples of Hclk
clock cycles. It is the time required to carry out
all fixed row operations outlined in Figure 18.
a programmable value between 0 & 2047 repre-
senting the Row Delay Time in multiples of Hclk.
This parameter allows the Row Operation Cycle
time to be extended. (See the Row Delay High
and Row Delay Low registers).
New R
ning of the first frame after the UpdateSettings
bit is set in the UPDATE register.
is the end row address of the defined scan win-
dow. (See section 2.0)
is the start row address of the defined scan win-
dow. (Scan section 2.0).
is a Mode Factor which must be applied. It is
dependent on the selected mode of operation as
shown in the table below:
is the Number of Rows in Selected Scan Win-
dow.
a programmable value between 0 & 4096 repre-
senting the Inter Frame Delay in multiples of
RN
be extended. (See the Frame Delay High and
Frame Delay Low registers).
New F
ning of the first frame after the UpdateSettings
bit is set in the UPDATE register.
RN
Hclk
Progressive Scan
Vertical Sub-sampling or
Interlace
factor *
rows
Frame Rate =
Hclk
delay
delay
. This parameter allows the frame time to
= (RAD
= R
SWN
values only take effect at the begin-
values only take effect at the begin-
opcycle
rows
end
) + F
+ R
- RAD
FN
Hclk
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Hclk
delay
delay
start
]
) + 1
*
RN
Hclk
1
0.5