ql2009-1pq208c QuickLogic Corp, ql2009-1pq208c Datasheet
ql2009-1pq208c
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ql2009-1pq208c Summary of contents
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... OEs on all I/O pins Other Important Family Features -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 672 Logic Cells 3.3V and 5.0V pASIC 2 FPGA 3-35 QL2009 Rev ...
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... The QL2009 is a 9,000 usable ASIC gate,16,000 usable PLD gate member of PRODUCT the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination SUMMARY of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices. The flexibility ...
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... QL2009 PIN # 1 PIN # 37 PIN # 1 PIN # 53 PINOUT DIAGRAMS 144-PIN TQFP pASIC QL2009-1PF144C 208-PIN PQFP pASIC QL2009-1PQ208C 3-37 PIN # 109 3 PIN # 73 PIN # 157 PIN # 105 ...
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... I/O 118 82 I/O I/O 119 NC I/O GND 120 83 I/O I/O 121 NC I/O I/O 122 84 I/O I/O 123 85 I/O I/O 124 NC I/O VCC 125 86 I/O I/O 126 NC I/O 3-38 QL2009 208 144 Function 208 144 PQFP TQFP 127 87 GND 169 117 128 88 I/O 170 118 129 89 I 171 119 130 90 ACLK / I 172 120 131 91 VCC 173 NC 132 92 I 174 NC 133 ...
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... QL2009 PINOUT DIAGRAM 256-PIN PBGA pASIC QL2009-1PB256C TOP BOTTOM 3-39 PIN A1 CORNER ...
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... J19 I/O R2 I/O J20 GCLK / I R3 I/O K1 I/O R4 VCC K2 I/O R17 VCC K3 I/O R18 I/O K4 VCC R19 I/O K17 I R20 I/O K18 ACLK / I T1 I/O K19 I T2 I/O K20 I I/O 3-40 QL2009 256 Function 256 Function PBGA PBGA T17 I/O V20 I/O T18 I/O W1 I/O T19 I/O W2 I/O T20 I/O W3 TDI U1 I/O W4 I/O U2 I/O W5 I/O U3 I/O W6 I/O U4 VSS W7 I/O U5 I/O W8 I/O U6 VCC ...
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... QL2009 Pin Function TDI Test Data In for JTAG TRSTB Active low Reset for JTAG TMS Test Mode Select for JTAG TCK Test Clock for JTAG TDO Test data out for JTAG STM Special Test Mode I/ACLK High-drive input and/or array network driver ...
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... Lead Temperature ………….………………. 300 C Industrial Min 4.5 -40 -X Speed Grade 0.4 -0 Speed Grade 0.4 -1 Speed Grade 0.4 -2 Speed Grade 0.4 Conditions IOH = -4 mA IOH = -24 mA/-16 mA [1] IOH = -10 A IOL = 24 mA/16 mA [1] IOL = VCC or GND VI = VCC or GND VO = GND VO = VCC VI, VIO = VCC or GND 3-42 QL2009 Commercial Unit Max Min Max 5.5 4.75 5. 2.75 0.46 2.55 2.00 0.46 1.85 1.61 0.46 1.50 1.35 ...
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... QL2009 3.3 Volt OPERATING RANGE Symbol Parameter VCC Supply Voltage TA Ambient Temperature -0 Speed Grade K Delay Factor -1 Speed Grade -2 Speed Grade DC CHARACTERISTICS over 3.3V operating range Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VOH Output HIGH Voltage VOL Output LOW Voltage ...
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... These limits are derived from a representative selection of the slowest paths through the pASIC 2 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. Propagation Delays (ns) Fanout [ 1.4 1.7 2.0 1.8 1.8 1.8 0.0 0.0 0.0 0.8 1.1 1.4 2.0 2.0 2.0 2.0 2.0 2.0 1.4 1.7 2.0 1.2 1.5 1.8 1.9 1.9 1.9 1.8 1.8 1.8 Propagation Delays (ns) Fanout [ 2.5 2.6 2.6 2.7 2.6 2.7 2.7 2.8 4.8 4.8 4.8 4.8 0.0 0.0 0.0 0.0 0.9 1.0 1.0 1.1 0.8 0.9 0.9 1.0 4.1 4.1 4.1 4.1 0.0 0.0 0.0 0.0 3-44 QL2009 4 8 2.3 3.5 1.8 1.8 0.0 0.0 1.7 2.9 2.0 2.0 2.0 2.0 2.3 3.5 2.1 3.3 1.9 1.9 1.8 1 3.5 4.6 5.8 3.6 4.7 5.9 4.8 4.8 4.8 0.0 0.0 0.0 1.9 3.0 4.2 1.8 2.9 4.1 4.1 4.1 4.1 0.0 0.0 0.0 ...
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... QL2009 Clock Cells Symbol Parameter tACK Array Clock Delay tGCKP Global Clock Pin Delay tGCKB Global Clock Buffer Delay I/O Cells Symbol Parameter tI/O Input Delay (bidirectional pad) tISU Input Register Set-Up Time tIH Input Register Hold Time tlOCLK Input Register Clock To Q tlORST ...
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... QL2009 ...