DS2465 MAXIM [Maxim Integrated Products], DS2465 Datasheet - Page 4

• Manufacturer Part Number: DS2465
• Description: SHA-256 Coprocessor with 1-Wire Master Function
• Manufacturer: MAXIM [Maxim Integrated Products]

ELECTRICAL CHARACTERISTICS (continued)
(T
Note 1: Limits are 100% production tested at T
Note 2: Operating current with 1-Wire write byte sequence followed by continuous read of 1-Wire Master Status register at 400kHz
Note 3: Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 4: Active pullup or resistive pullup and range are configurable.
Note 5: The active pullup does not apply to the rising edge of a presence pulse outside of a 1-Wire Reset Pulse command or
Note 6: All 1-Wire timing specifications are derived from the same timing circuit.
Note 7: Current drawn from V
Note 8: Write-cycle endurance is tested in compliance with JESD47G.
Note 9: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 10: Data retention is tested in compliance with JESD47G.
Note 11: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
Note 12: I
Note 13: All I
Note 14: I/O pins of the DS2465 do not obstruct the SDA and SCL lines if V
Note 15: The DS2465 provides a hold time of at least 300ns for the SDA signal (referenced to the V
Note 16: The maximum t
Note 17: A fast-mode I
Note 18: C
Input Capacitance
SCL Clock Frequency
Hold Time (Repeated) START
Condition; After this Period, the
First Clock Pulse is Generated
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a STOP
and START Condition
Capacitive Load for Each Bus Line
Oscillator Warmup Time
SHA-256 Coprocessor with 1-Wire Master Function
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
in overdrive.
during the recovery after a short on the 1-Wire line.
data sheet limit at operating temperature range is established by reliability testing.
from sleep mode.
bridge the undefined region of the falling edge of SCL.
clock stretches the SCL, the data must be valid by the setup time before it releases the clock (I
Rev. 03, 19 June 2007).
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
250 = 1250ns (according to the standard-mode I
edge timing must meet this setup time (I
ing on the actual operating voltage and frequency of the application (I
2
PARAMETER
C communication should not take place for the max t
B
= Total capacitance of one bus line in pF. The maximum bus capacitance allowable may vary from this value depend-
2
C timing values are referred to V
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2
C bus device can be used in a standard-mode I
HD:DAT
CC
has only to be met if the device does not stretch the low period (t
during the EEPROM programming interval or SHA-256 computation.
SYMBOL
t
t
OSCWUP
t
t
t
t
HD:STA
HD:DAT
SU:DAT
SU:STO
SU:STA
t
t
f
HIGH
t
LOW
SCL
BUF
C
C
B
I
IH(MIN)
A
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Notes 3, 15, 16)
(Notes 3, 17)
(Note 3)
(Note 3)
(Notes 3, 18)
(Note 12)
2
= +25°C and/or T
C bus specification Rev. 03, 19 June 2007).
and V
2
C bus specification) before the SCL line is released. Also the acknowl-
IL(MAX)
CONDITIONS
OSCWUP
A
levels.
= +85°C. Limits over the operating temperature range and
2
or t
C-bus system, but the requirement t
CC
SWUP
is switched off.
2
C bus specification Rev. 03, 19 June 2007).
time following a power-on reset or a wake-up
MIN
250
0.6
1.3
0.6
0.6
0.6
1.3
0
LOW
IH(MIN)
) of the SCL signal. If the
R(MAX)
TYP
2
C bus specification
of the SCL signal) to
SU:DAT
+ t
DS2465
SU:DAT
MAX
400
400
200
0.9
10
R 250ns must
= 1000 +
UNITS
kHz
pF
pF
Fs
Fs
Fs
Fs
Fs
ns
Fs
Fs
Fs