DS1865T+TR MAXIM [Maxim Integrated Products], DS1865T+TR Datasheet - Page 33
DS1865T+TR
Manufacturer Part Number
DS1865T+TR
Description
PON Triplexer Control and Monitoring Circuit
Manufacturer
MAXIM [Maxim Integrated Products]
Datasheet
1.DS1865TTR.pdf
(66 pages)
- Current page: 33 of 66
- Download datasheet (531Kb)
Lower Memory, Register 6Eh: Status
POWER-ON VALUE
READ ACCESS
WRITE ACCESS
MEMORY TYPE:
W r i te Access
6Eh
STATUS
FETG
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
N/A
bit7
FETG STATUS: Reflects the active state of FETG. The FETG-DIR bit in Table 02h, Register 89h
defines the polarity of FETG.
0 = Normal operation. Bias and modulation outputs are enabled.
1 = The FETG output is active. Bias and modulation outputs are disabled.
SOFT FETG:
0 = (Default)
1 = Forces the bias and modulation outputs to their off states and asserts the FETG output.
RESERVED (Default = 0)
TX-F RESET:
0 = Does not affect the TX-F output. (Default)
1 = Resets the latch for the TX-F output. This bit is self-clearing after the reset.
SOFT TX-D: This bit allows a software control is identical to the TX-D pin. See the section on TX-D for
further information. Its value is wired-ORed with the logic value of the TX-D pin.
0 = Internal TX-D signal is equal to external TX-D pin.
1 = Internal TX-D signal is high.
TX-F STATUS: Reflects the active state of TX-F.
0 = TX-F pin is not active.
1 = TX-F pin is active.
LOS STATUS: Loss of Signal. Reflects the logic level of the D0 input pin. Note that with the use of the
MUX LOSI and INV LOSI bits (Table 02h, Register C0h), the D0 pin is controlled by the LOSI pin.
0 = D0 is logic-low.
1 = D0 is logic-high.
RDYB: Ready Bar.
0 = V
1 = V
SOFT
FETG
ALL
x000 0x0x b
All
See Below
Volatile
CC
CC
is above POA.
is below POA or too low to communicate over the I
____________________________________________________________________
RESERVED
N/A
PON Triplexer Control and
RESET
TX-F
ALL
SOFT
TX-D
ALL
Monitoring Circuit
2
C bus.
STATUS
TX-F
N/A
STATUS
LOS
N/A
RDYB
N/A
bit0
33
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