DS1865T+TR MAXIM [Maxim Integrated Products], DS1865T+TR Datasheet - Page 49
DS1865T+TR
Manufacturer Part Number
DS1865T+TR
Description
PON Triplexer Control and Monitoring Circuit
Manufacturer
MAXIM [Maxim Integrated Products]
Datasheet
1.DS1865TTR.pdf
(66 pages)
- Current page: 49 of 66
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Table 02h, Register 89h: Config
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE:
Configure the memory location and the polarity of the digital outputs.
Table 02h, Register 8Ah: Startup Step
FACTORY DEFAULT:
READ ACCESS
WRITE ACCESS
MEMORY TYPE:
This value will define the maximum allowed step for the upper 8 bits of I
cause the device to take single LSB (2
details.
8Ah
89h
FETG DIR
bit3:0
bit7
bit6
bit5
bit4
bit7
bit7
2
12
FETG DIR: Chooses the direction or polarity of the FETG output for normal operation.
0 = (Default) Under normal operation, FETG is pulled low. Intended for use with nMOS.
1 = Under normal operation, FETG is pulled high. Intended for use with pMOS.
TX-F EN: The TX-F output pin always reflects the wired-OR of all TXF enabled alarm states. This bit
will enable the latching of the alarm state for the TXF output pin.
0 = (Default) Not latched.
1 = The alarm bits are latched until cleared by a TX-D transition or power-down. If V
enabled for either FETG or TX-F then latching is disabled until the after the first V
made above the V
RESERVED
ASEL: Address Select.
0 = (Default) Device Address of A2h.
1 = I
(Table 02h, Register 8Ch).
RESERVED
TX-F EN
00h
PW2
PW2
00h
PW2
PW2
Nonvolatile (SEE)
2
Nonvolatile (SEE)
2
11
C slave address is determined by the value programmed in the DEVICE ADDRESS byte
0
) steps towards convergence. See the BIAS and MOD Output During Power-Up section for
____________________________________________________________________
RESERVED
CC
2
10
_Lo set point to allow for proper operation during slow power-on cycles.
PON Triplexer Control and
ASEL
2
9
BIAS
RESERVED
output during startup. Programming this value to 00h
2
8
Monitoring Circuit
RESERVED
2
7
RESERVED
2
6
CC
measurement is
CC
_Lo_Alarm is
RESERVED
bit0
bit0
2
5
49
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