DS1876T+TR MAXIM [Maxim Integrated Products], DS1876T+TR Datasheet - Page 37
DS1876T+TR
Manufacturer Part Number
DS1876T+TR
Description
SFP Controller with Dual LDD Interface
Manufacturer
MAXIM [Maxim Integrated Products]
Datasheet
1.DS1876TTR.pdf
(69 pages)
- Current page: 37 of 69
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Lower Memory, Register 71h: ALARM
Lower Memory, Register 72h: ALARM
71h
72h
POWER-ON VALUE
READ ACCESS
WRITE ACCESS
A2h AND B2h MEMORY
MEMORY TYPE
RESERVED
POWER-ON VALUE
READ ACCESS
WRITE ACCESS
A2h AND B2h MEMORY
MEMORY TYPE
RESERVED
BITS 7:4, 2
BITS 7:3
BIT 7
BIT 2
BIT 1
BIT 0
BIT 7
BIT 3
BIT 1
BIT 0
______________________________________________________________________________________
SFP Controller with Dual LDD Interface
RESERVED
TXFOUTS: TXFOUT status. Indicates the state the open-drain output is attempting to achieve.
0 = TXFOUT is pulling low.
1 = TXFOUT is high impedance.
FETG: Status of internal signal FETG. The FETG signal is part of the internal shutdown logic.
0 = (default) FETG is low.
1 = FETG is high.
TXFINT: TXF interrupt. This bit is the wire-ORed logic of all alarms and warnings wire-ANDed with
their corresponding enable bits, plus the wire-ORed logic of HBAL, TXP HI, and TXP LO. The enable
bits are found in Table 01h/05h, Registers F8h–FFh.
RESERVED
RESERVED
HBAL: High bias alarm status; fast comparison. A TXD event clears this alarm.
0 = (default) Last comparison was below threshold setting.
1 = Last comparison was above threshold setting.
TXP HI: High alarm status TXP; fast comparison. A TXD event clears this alarm.
0 = (default) Last comparison was below threshold setting.
1 = Last comparison was above threshold setting.
TXP LO: Low alarm status TXP; fast comparison. A TXD event clears this alarm.
0 = (default) Last comparison was above threshold setting.
1 = Last comparison was below threshold setting.
RESERVED
RESERVED
RESERVED
2
1
00h
All
N/A
Mixed A2h and B2h memory locations
Volatile
00h
All
N/A
Different A2h and B2h memory locations
Volatile
RESERVED
RESERVED
RESERVED
HBAL
<C>
RESERVED
TXFOUTS
<D>
TXP HI
FETG
<D>
TXP LO
BIT 0
BIT 0
TXFINT
37
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