A25L05P AMICC [AMIC Technology], A25L05P Datasheet - Page 28

• Manufacturer Part Number: A25L05P
• Description: 2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
• Manufacturer: AMICC [AMIC Technology]

POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be
selected (that is Chip Select (
applied on V
­
­
Usually a simple pull-up resistor on Chip Select (
used to insure safe and proper Power-up and Power-down.
To avoid data corruption and inadvertent write operations
during power up, a Power On Reset (POR) circuit is included.
The logic inside the device is held reset while V
the POR threshold value, V
and the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page
Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write
Status Register (WRSR) instructions until a time delay of t
has elapsed after the moment that V
threshold. However, the correct operation of the device is not
guaranteed if, by this time, V
Write Status Register, Program or Erase instructions should
be sent until the later of:
Figure 19. Power-up Timing
(August, 2007, Version 1.0)
V
V
CC
SS
(min) at Power-up, and then for a further delay of t
at Power-down
CC
) until V
CC
V
reaches the correct value:
V
CC
CC
WI
(min)
(max)
CC
– all operations are disabled,
S
V
is still below V
) must follow the voltage
CC
CC
rises above the VWI
CC
CC
is less than
S
(min). No
) can be
VSL
PUW
t
PU
27
­
- t
These values are specified in Table 9.
If the delay, t
V
even if the t
At Power-up, the device is in the following state:
­
­
Normal precautions must be taken for supply rail decoupling,
to stabilize the V
have the V
the package pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when V
to below the POR threshold value, V
disabled and the device does not respond to any instruction.
(The designer needs to be aware that if a Power-down occurs
while a Write, Program or Erase cycle is in progress, some
data corruption can result.)
CC
t
A25L20P/A25L10P/A25L05P Series
The device is in the Standby mode (not the Deep
Power-down mode).
The Write Enable Latch (WEL) bit is reset.
VSL
(min), the device can be selected for READ instructions
PUW
afterV
after V
Full Device Access
CC
PUW
CC
rail decoupled by a suitable capacitor close to
CC
VS L
delay is not yet fully elapsed.
passed the V
passed the VWI threshold
, has elapsed, after V
CC
feed. Each device in a system should
CC
AMIC Technology Corp.
drops from the operating voltage,
CC
(min) level
time
WI
CC
, all operations are
has risen above