CY2308-1 CYPRESS [Cypress Semiconductor], CY2308-1 Datasheet - Page 3

• Manufacturer Part Number: CY2308-1
• Description: 3.3V Zero Delay Buffer
• Manufacturer: CYPRESS [Cypress Semiconductor]

Available CY2308 Configurations
Zero Delay and Skew Control
Table 2. REF. Input to CLKA/CLKB Delay Versus Difference in Loading between FBK pin and CLKA/CLKB Pins
To close the feedback loop of the CY2308, the FBK pin is driven
from any of the eight available output pins. The output driving the
FBK pin drives a total load of 7 pF plus any additional load that
it drives. The relative loading of this output to the remaining
outputs adjusts the input-output delay. This is shown in the
Table
For applications requiring zero input-output delay, all outputs
including the one providing feedback is equally loaded.
Document Number: 38-07146 Rev. *E
Note
CY2308–1
CY2308–1H
CY2308–2
CY2308–2
CY2308–3
CY2308–3
CY2308–4
CY2308–5H
5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2.
2.
Device
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Feedback From
Reference
Reference
Reference
2 X Reference
2 X Reference
4 X Reference
2 X Reference
Reference /2
Bank A Frequency
If input-output delay adjustments are required, use the
Delay and Skew Control
between the feedback output and remaining outputs.
For zero output-output skew, outputs are loaded equally. For
further information on using CY2308, refer to the application note
“CY2308: Zero Delay Buffer.”
Reference
Reference
Reference/2
Reference
Reference or Reference
2 X Reference
2 X Reference
Reference /2
graph to calculate loading differences
Bank B Frequency
[5]
CY2308
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Zero
[+] Feedback