CY25010 CYPRESS [Cypress Semiconductor], CY25010 Datasheet - Page 5

• Manufacturer Part Number: CY25010
• Manufacturer: CYPRESS [Cypress Semiconductor]

Spread Aware™
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we
designed this product so as not to filter off the Spread Spectrum
feature of the Reference input, assuming it exists. When a zero
delay buffer is not designed to pass the SS feature through, the
result is a significant amount of tracking skew which may cause
problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology, please
see the Cypress application note titled, “EMI Suppression
Techniques with SSFTG ICs.”
How to Implement Zero Delay
Typically, Zero Delay Buffers (ZDBs) are used because a
designer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve this, layout
must compensate for trace length between the ZDB and the
target devices. The method of compensation is described below.
External feedback is the trait that allows for this compensation.
Since the PLL on the ZDB will cause the feedback signal to be
in phase with the reference signal. When laying out the board,
match the trace lengths between the output being used for feed
back and the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly precede the
input signal, this may also be affected by either making the trace
to the FBIN pin a little shorter or a little longer than the traces to
the devices being clocked.
Document Number: 38-07230 Rev. *E
V
V
DD
DD
0.1 F
0.1 F
Figure 1. CY2510 Example Schematic
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2
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7
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9
AGND
VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE
FBOUT
AVDD
FBIN
GND
GND
VDD
VDD
CLK
Q9
Q8
Q7
Q6
Q5
Inserting Other Devices in Feedback Path
Another nice feature available due to the external feedback is the
ability to synchronize signals up to the signal coming from some
other device. This implementation can be applied to any device
(ASIC, multiple output clock buffer/driver, etc.) which is put into
the feedback path.
Referring to
the destination of the clock signal(s) (A) are equal in length to the
trace between the buffer and the FBIN pin, the signals at the
destination(s) device will be driven HIGH at the same time the
Reference clock provided to the ZDB goes HIGH. Synchronizing
the other outputs of the ZDB to the outputs form the ASIC/Buffer
is more complex however, as any propagation delay in the
ASIC/Buffer must be accounted for.
Figure 2. Additional Buffering Feedback Path Example
Schematic
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13
Reference
Feedback
0.1 F
Signal
Input
Figure
10 F
2, if the traces between the ASIC/buffer and
0.1 F
Zero
Delay
Buffer
0.1 F
VDD
10 F
FB
FB
V
Buffer
ASIC/
DD
3.3V
CY2509/10
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