CY28412OC SPECTRALINEAR [SpectraLinear Inc], CY28412OC Datasheet - Page 9

• Manufacturer Part Number: CY28412OC
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 20, 2006
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
PCI, 33 MHz
USB, 48MHz
DOT96C
DOT96T
REF
PD
Cs1
Figure 3. Power-down Assertion Timing Waveform
Figure 2. Crystal Loading Example
Ce1
X1
Ci1
Clock Chip
XTAL
Ci2
clock chip. All differential outputs stopped in a tristate condition
resulting from power down must be driven high in less than
300 s of PD deassertion to a voltage greater than 200 mV.
After the clock chip’s internal PLL is powered up and locked,
all outputs are enabled within a few clock cycles of each other.
X2
Ce2
Cs2
3 to 6p
33pF
Pin
Trim
2.8pF
Trace
CY28412
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