CY28442-2_05 CYPRESS [Cypress Semiconductor], CY28442-2_05 Datasheet - Page 7

• Manufacturer Part Number: CY28442-2_05
• Description: Clock Generator for Intel Alviso Chipset
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-07691 Rev. *B
Byte 5: Control Register 5 (continued)
Byte 6: Control Register 6
Byte 7: Vendor ID
Byte 8: Control Register 8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
Bit
Bit
Bit
Bit
1
0
7
6
5
4
3
2
0
@Pup
@Pup
@Pup
@Pup
HW
HW
HW
0
0
0
0
1
1
0
1
0
0
0
1
0
0
0
0
1
0
0
0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
CLKREQ#B
CLKREQ#B
CLKREQ#B
CLKREQ#B
RESERVED
CLKREQ#A
PCI, PCIF and SRC clock
outputs except those set
to free running
TEST_MODE
RESERVED
TEST_SEL
CPU[T/C]0
Name
Name
Name
FS_C
Name
FS_B
FS_A
REF
REF/N or Tri-state Select
0 = Tri-state, 1 = REF/N Clock
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Tri-state mode,
RESERVED
REF Output Drive Strength
0 = Low, 1 = High
SW PCI_STP Function
0=SW PCI_STP assert, 1= SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
FS_C Reflects the value of the FS_C pin sampled on power-up
0 = FS_C was low during VTT_PWRGD# assertion
FS_B Reflects the value of the FS_B pin sampled on power-up
0 = FS_B was low during VTT_PWRGD# assertion
FS_A Reflects the value of the FS_A pin sampled on power-up
0 = FS_A was low during VTT_PWRGD# assertion
SRC[T/C]7CLKREQ#B control
1 = SRC[T/C]7 stoppable by CLKREQ#B pin
0 = SRC[T/C]7 not controlled by CLKREQ#B pin
SRC[T/C]5 CLKREQ#B control
1 = SRC[T/C]5 stoppable by CLKREQ#B pin
0 = SRC[T/C]5 not controlled by CLKREQ#B pin
SRC[T/C]3 CLKREQ#B control
1 = SRC[T/C]3 stoppable by CLKREQ#B pin
0 = SRC[T/C]3 not controlled by CLKREQ#B pin
SRC[T/C]1 CLKREQ#B control
1 = SRC[T/C]1 stoppable by CLKREQ#B pin
0 = SRC[T/C]1 not controlled by CLKREQ#B pin
RESERVED
SRC[T/C]4 CLKREQ#A control
1 = SRC[T/C]4 stoppable by CLKREQ#A pin
0 = SRC[T/C]4 not controlled by CLKREQ#A pin
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Description
Description
Description
CY28442-2
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