FS6377-01 American Microsystems, Inc., FS6377-01 Datasheet - Page 16

• Manufacturer Part Number: FS6377-01
• Description: Programmable 3-pll Clock Generator ic
• Manufacturer: American Microsystems, Inc.

FS6377-01
FS6377-01
Programmable 3-PLL Clock Generator IC
Programmable 3-PLL Clock Generator IC
Table 16: AC Timing Specifications, continued
Unless otherwise stated, V
data and are not currently production tested to any specific limits. MIN and MAX characterization data are
FS6377-01
FS6377-01
Programmable 3-PLL Clock Generator IC
Programmable 3-PLL Clock Generator IC
Clock Outputs (PLL B clock via CLK_B pin)
Clock Outputs (PLL_C clock via CLK_C pin)
Clock Outputs (Crystal Oscillator via CLK_D pin)
ISO9001
ISO9001
ISO9001
ISO9001
Duty Cycle *
Jitter, Long Term (
Jitter, Period (peak-peak) *
Duty Cycle *
Jitter, Long Term (
Jitter, Period (peak-peak) *
Duty Cycle *
Jitter, Long Term (
Jitter, Period (peak-peak) *
PARAMETER
DD
y
y
y
= 5.0V ± 10%, no load on any output, and ambient temperature range T
( )) *
( )) *
( )) *
SYMBOL
t
t
t
t
t
t
j(LT)
j( P)
j(LT)
j( P)
j(LT)
j( P)
Ratio of pulse width (as measured from rising edge to
next falling edge at 2.5V) to one clock period
On rising edges 500 s apart at 2.5V relative to an ideal
clock, C
N
On rising edges 500 s apart at 2.5V relative to an ideal
clock, C
N
D=14.318MHz)
From rising edge to the next rising edge at 2.5V,
C
No other PLLs active
From rising edge to the next rising edge at 2.5V,
C
other PLLs active (A=50MHz, C=40MHz, D=14.318MHz)
Ratio of pulse width (as measured from rising edge to
next falling edge at 2.5V) to one clock period
On rising edges 500 s apart at 2.5V relative to an ideal
clock, C
N
On rising edges 500 s apart at 2.5V relative to an ideal
clock, C
N
D=14.318MHz)
From rising edge to the next rising edge at 2.5V,
C
No other PLLs active
From rising edge to the next rising edge at 2.5V,
C
other PLLs active (A=50MHz, B=60MHz, D=14.318MHz)
Ratio of pulse width (as measured from rising edge to
next falling edge at 2.5V) to one clock period
On rising edges 500 s apart at 2.5V relative to an ideal
clock, C
From rising edge to the next rising edge at 2.5V,
C
(A=50MHz, B=60MHz, C=40MHz)
From rising edge to the next rising edge at 2.5V,
C
From rising edge to the next rising edge at 2.5V,
C
(A=50MHz, B=60MHz, C=40MHz)
Px
Px
L
L
Px
Px
L
L
L
L
L
=15pF, f
=15pF, f
=15pF, f
=15pF, f
=15pF, f
=15pF, f
=15pF, f
=50, No other PLLs active
=50, all other PLLs active (A=50MHz, C=40MHz,
=50, No other PLLs active
=50, all other PLLs active (A=50MHz, B=60MHz,
L
L
L
L
L
CONDITIONS/DESCRIPTION
=15pF, f
=15pF, f
=15pF, f
=15pF, f
=15pF, f
XIN
XIN
XIN
XIN
XIN
XIN
XIN
=14.318MHz, N
=14.318MHz, N
=14.318MHz, N
=14.318MHz, N
=14.318MHz, all other PLLs active
=14.318MHz, No other PLLs active
=14.318MHz, all other PLLs active
XIN
XIN
XIN
XIN
XIN
=14.318MHz, N
=14.318MHz, N
=14.318MHz, N
=14.318MHz, N
=14.318MHz, No other PLLs active
16
F
F
F
F
=220, N
=220, N
=220, N
=220, N
A
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
F
F
F
F
3 from typical.
=220, N
=220, N
=220, N
=220, N
R
R
R
R
=63, N
=63, N
=63, N
=63, N
R
R
R
R
=63,
=63,
=63,
=63,
Px
Px
Px
Px
=50,
=50, all
=50,
=50, all
CLOCK
14.318
14.318
14.318
14.318
14.318
(MHz)
100
100
100
100
100
100
60
60
40
40
MIN.
45
45
45
TYP.
120
400
105
120
440
450
45
75
45
20
40
90
MAX.
55
55
55
UNITS
11.22.02
ps
ps
ps
ps
ps
ps
%
%
%