FS6377-01 American Microsystems, Inc., FS6377-01 Datasheet - Page 8

• Manufacturer Part Number: FS6377-01
• Description: Programmable 3-pll Clock Generator ic
• Manufacturer: American Microsystems, Inc.

FS6377-01
FS6377-01
Programmable 3-PLL Clock Generator IC
Programmable 3-PLL Clock Generator IC
7.0
Table 3: Register Map
7.1
If any PLL control bit is altered during device operation,
including those bits controlling the Reference and Feed-
back Dividers, the output frequency will slew smoothly (in
a glitch-free manner) to the new frequency. The slew rate
is related to the programmed loop filter time constant.
However, any programming changes to any Mux or Post
Divider control bits will cause a glitch on an operating
clock output.
7.1.1
All power-down functions are controlled by enable bits.
The bits select which portions of the device to power-
down when the PD input is asserted.
FS6377-01
FS6377-01
Programmable 3-PLL Clock Generator IC
Programmable 3-PLL Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
ADDRESS
BYTE 15
BYTE 14
BYTE 13
BYTE 12
BYTE 11
BYTE 10
BYTE 9
BYTE 8
BYTE 7
BYTE 6
BYTE 5
BYTE 4
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Programming Information
Control Bit Assignment
Power Down
(selected via SEL_CD = 1)
(selected via SEL_CD = 0)
(selected via SEL_CD = 0)
BIT 7
MUX_D2[1:0]
MUX_D1[1:0]
MUX_C1[1:0]
MUX_B[1:0]
MUX_A[1:0]
(Note: All Register Bits are cleared to zero on power-up.)
(selected via SEL_CD = 1)
(selected via SEL_CD = 0)
BIT 6
POST_D2[3:0]
POST_D1[3:0]
(selected via SEL_CD pin = 1)
POST_B[3:0]
FBKDIV_C2[7:3] M-Counter
FBKDIV_C1[7:3] M-Counter
FBKDIV_B[7:3] M-Counter
FBKDIV_A[7:3] M-Counter
(selected via SEL_CD = 0)
Reserved (0)
(selected via SEL_CD = 1)
PDPLL_C
PDPLL_B
PDPLL_A
BIT 5
MUX_C2[1:0]
(selected via SEL_CD pin = 1)
(SEL_CD=1)
(SEL_CD=0)
(selected via SEL_CD = 0)
LFTC_C2
LFTC_C1
LFTC_B
LFTC_A
BIT 4
8
REFDIV_C2[7:0]
REFDIV_C1[7:0]
REFDIV_B[7:0]
REFDIV_A[7:0]
Table 4: Power-Down Bits
Reserved (0)
PDPLL_A
PDPLL_B
PDPLL_C
(Bit 21)
(Bit 45)
(Bit 69)
(Bit 69)
NAME
(SEL_CD=1)
(SEL_CD=0)
PDPOST_D
CP_C2
CP_C1
CP_B
CP_A
BIT 3
Power-Down PLL A
Bit = 0
Bit = 1
Power-Down PLL B
Bit = 0
Bit = 1
Power-Down PLL C
Bit = 0
Bit = 1
Set these reserved bits to zero (0)
PDPOST_C
(selected via SEL_CD = 1)
(selected via SEL_CD = 0)
BIT 2
POST_C2[3:0]
POST_C1[3:0]
FBKDIV_C2[10:8] M-Counter
FBKDIV_C1[10:8] M-Counter
(selected via SEL_CD pin = 1)
(selected via SEL_CD pin = 1)
POST_A[3:0]
FBKDIV_C2[2:0] A-Counter
FBKDIV_C1[2:0] A-Counter
FBKDIV_B[10:8] M-Counter
FBKDIV_A[10:8] M-Counter
FBKDIV_B[2:0] A-Counter
FBKDIV_A[2:0] A-Counter
(selected via SEL_CD = 0)
(selected via SEL_CD = 1)
DESCRIPTION
Power On
Power Off
Power On
Power Off
Power On
Power Off
PDPOST_B
BIT 1
PDPOST_A
BIT 0
11.22.02