FS7140-01 AMI [AMI SEMICONDUCTOR], FS7140-01 Datasheet
FS7140-01
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FS7140-01 Summary of contents
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator 1.0 Features • Extremely flexible and low-jitter phase-locked loop (PLL) frequency synthesis • No external loop filter components needed • 150MHz CMOS or 340MHz PECL outputs • Completely configurable via I C™-bus 2 • four FS7140 or FS7145 can be used on a single ...
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Table 1: FS7140 Pin Descriptions Pin Type DIO Key Analog Input Analog Output Digital Input; DI DI-3 = Three-Level Digital Input Digital Output Power/Ground Active Low pin ...
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator 4.0 Functional Block Description 4.1 Phase Locked Loop (PLL) The phase locked loop is a standard phase- and frequency- locked loop architecture. The PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), a feedback divider, and a post divider ...
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator not connect OUT When not using the REF input preferred to leave it floating or connected 4.1.6 Feedback Divider Source MUX The source of frequency for the feedback divider may be selected to be either the output of the post divider or the output of the VCO by the FBKDSRC bit ...
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator 5.1 Bus Conditions Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START or STOP condition ...
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator acknowledge the transfer but does generate a STOP condition. 5.2.4 Sequential Register Write Procedure Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after each write. This procedure is more efficient than the random register write if several registers must be written ...
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator S DEVICE ADDRESS W A REGISTER ADDRESS 7-bit Receive Register Address Device Address Acknowledge START WRITE Command Command From bus host to device Figure 4: Random Register Write Procedure S DEVICE ADDRESS W A REGISTER ADDRESS 7-bit Receive Register Address ...
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator 6.0 Programming Information All register bits are cleared to zero on power-up. All register bits may be read back as written. Table 3: FS7140 Register Map ADDRESS BIT 7 RESERVED RESERVED (Bit 63) BYTE 7 Must be set to “0” Must be set to “0” ...
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Table 4: FS7145 Register Map ADDRESS BIT 7 RESERVED RESERVED BYTE 7 (Bit 63) Must be set to “0” Must be set to “0” RESERVED RESERVED (Bit 55) BYTE 6 Must be set to “0” Must be set to “0” RESERVED (Bit 47) ...
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Table 5: Device Configuration Bits Name Description REFerence Divider SouRCe REFDSRC [0] = Crystal Oscillator / [1] = REF Pin FeedB ack Divider SouRCe FBKDSRC [0] = VCO Output / [1] = Post Divider Output SHUTdown1 SHUT1 [0] = Normal / [1] = Powered Down SHUTdown2 SHUT2 [0] = Normal / [1] = Powered Down ...
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator 7.0 Electrical Specifications Table 10: Absolute Maximum Ratings Parameter Supply Voltage ground) SS Input Voltage, dc Output Voltage, dc Input Clamp Current < Output Clamp Current < Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias ...
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Table 12: DC Electrical Specifications Parameter Overall Supply Current, Dynamic Supply Current, Static Serial Communication I/O (SDA, SCL) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage Input Leakage Current Low-Level Output Sink Current (SDA) Address Select Input (ADDR0, ADDR1) ...
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Table 13: AC Timing Specifications Parameter Overall Output Frequency* VCO Frequency* CMOS Mode Rise Time* CMOS Mode Fall Time* PECL Mode Rise Time* PECL Mode Fall Time* Reference Frequency Input (REF) Input Frequency Reference High Time ...
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator SCL t su:STA SDA START t F SCL t su:STA t hd:STA SDA IN SDA OUT 8.0 Package Information for ‘Green’ (FS7140) and ‘Non-Green’ (FS7140 & FS7145) Table 15: 16-pin SOIC (0.150”) Package Dimensions Dimensions Inches Min. ...
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... FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Table 16: 16-pin SOIC (0.150”) Package Characteristics Parameter Thermal Impedance, Junction to Free-Air Lead Inductance, Self Table 17: 16-pin 5.3mm (0.209”) SSOP Package Dimensions Dimensions Inches Min. Max. Min. A 0.068 0.078 1.73 A1 0.002 0.008 0.05 A2 0.066 ...