CS4239-JQ CIRRUS [Cirrus Logic], CS4239-JQ Datasheet - Page 90

• Manufacturer Part Number: CS4239-JQ
• Manufacturer: CIRRUS [Cirrus Logic]

Volume Control
UP - Volume Up - Internal Pullup
DOWN - Volume Down - Internal Pullup
MUTE - Volume Mute - Internal Pullup
Miscellaneous
XTALI - Crystal Input
XTALO - Crystal Output
APSEL - Address Port Select, Input
TEST - Test
90
The volume control pins are enabled by setting VCEN in the Hardware Configuration data,
Misc. Hardware Config. byte. The VCF1 bit in the Hardware Configuration data, Global
Configuration byte, set the format for the volume control pins. Typically a 100
and a 10 nF capacitor (required) to ground, capacitor on the switch side of the series resistor,
would be included on each pin for ESD protection and to help with EMI emissions.
This pin is enabled when VCEN is set. When UP is low, the master volume output for left and
right channels are incremented. A 10 nF capacitor to ground is required for switch debounce.
The XCTL1/ACDCS/DOWN is a multiplexed pin that can be used as XCTL1, the alternate
CDROM chip select, or the Volume Down pin. This pin is switched to the DOWN function
when VCEN is set. When DOWN is low, the master volume output for left and right channels
are decremented. A 10 nF capacitor to ground is required for switch debounce.
The MUTE pin function can be momentary, or non-existent based on the VCF1 bit. The MUTE
function is enabled when VCEN is set. A 10 nF capacitor to ground is required for switch
debounce.
This pin will accept either a crystal, with the other pin attached to XTALO, or an external
CMOS clock. XTAL must have a crystal or clock source attached for proper operation. The
crystal frequency must be 16.9344 MHz and designed for fundamental mode, parallel resonance
operation.
This pin is used for a crystal placed between this pin and XTALI. If an external clock is used
on XTALI, this pin must be left floating with no traces or components connected to it.
This pin has an internal pull-up of approximately 100 k . Leaving this pin in its default
condition, places the PnP/Crystal Key Address Port at the standard PnP address of 279h (hex).
For Motherboard applications, APSEL can be tied to SGND, which will change the Address
Port to one of two other addresses, chosen by a strapping option on pin SCL. When RESDRV
goes inactive, pin SCL is forced to an input and sampled. When SCL is sampled high (default),
the Address Port changes to address 308h. When SCL is sampled low, the Address Port changes
to 388h. Add-in cards should leave APSEL unconnected.
This pin must be tied to ground for proper operation.
CrystalClear Portable ISA Audio System
TM
series resistor
CS4239
DS253PP2