CS42426_05 CIRRUS [Cirrus Logic], CS42426_05 Datasheet - Page 55
CS42426_05
Manufacturer Part Number
CS42426_05
Description
114 dB, 192 kHz 6-Ch Codec with PLL
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
1.CS42426_05.pdf
(73 pages)
- Current page: 55 of 73
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DS604F1
6.15
6.15.1 ADC LEFT CHANNEL GAIN (LGAINX)
6.16
6.16.1 ADC RIGHT CHANNEL GAIN (RGAINX)
6.17
6.17.1 SERIAL PORT SYNCHRONIZATION (SP_SYNC)
SP_SYNC
Reserved
Reserved
7
7
7
ADC Left Channel Gain (address 1Ch)
ADC Right Channel Gain (address 1Dh)
Interrupt Control (address 1Eh)
Default = 00h
Function:
Default = 00h
Function:
The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in
The level of the right analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in
Default = 0
0 - DAC & ADC Serial Port timings not in phase
1 - DAC & ADC Serial Port timings are in phase
Function:
Forces the LRCK and SCLK from the DAC & ADC Serial Ports to align and operate in phase. This
function will operate when both ports are running at the same sample rate or when operating at dif-
ferent sample rates.
Table
Table
Reserved
Reserved
Reserved
6
6
6
15.
15.
Binary Code
001010
000101
000000
110110
110001
001111
111011
DE-EMPH1
RGAIN5
LGAIN5
Table 15. Example ADC Input Gain Settings
5
5
5
DE-EMPH0
RGAIN4
LGAIN4
Decimal Value
4
4
4
+15
+10
-10
-15
+5
-5
0
RGAIN3
LGAIN3
INT1
3
3
3
Volume Setting
RGAIN2
LGAIN2
+15 dB
+10 dB
-10 dB
-15 dB
+5 dB
-5 dB
0 dB
INT0
2
2
2
Reserved
RGAIN1
LGAIN1
1
1
1
CS42426
Reserved
RGAIN0
LGAIN0
0
0
0
55
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