CS82C86H INTERSIL [Intersil Corporation], CS82C86H Datasheet - Page 3

• Manufacturer Part Number: CS82C86H
• Description: CMOS Octal Bus Transceiver
• Manufacturer: INTERSIL [Intersil Corporation]

Functional Diagram
Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
V
ing threshold. Additionally, if the driving signal becomes high
impedance (“float” condition), it could create an indetermi-
nate logic state at the inputs and cause a disruption in
device operation.
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the device is
disabled (OE = logic one for the 82C86H/87H). These gated
inputs disconnect the input circuitry from the V
ground power supply pins by turning off the upper P-channel
and lower N-channel (See Figures 1 and 2). No current flow
from V
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device.
D.C. input voltage levels can also cause an increase in ICC if
these input levels approach the minimum V
V
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi-
tion will occur only during the time the device is in the trans-
parent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of 10 A during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.
CC
IL
conditions. This is due to the operation of the input cir-
and GND when the signal is at or near the input switch-
CC
to GND occurs during input transitions and invalid
OE
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
T
IH
or maximum
CC
82C86H
82C86H
and
4-319
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C86H/87H data
sheet is determined by:
I
Assuming that all outputs change state at the same time and
that dv/dt is constant;
I
where tR = 20ns, V
puts.
I
This current spike may cause a large negative voltage spike
on V
To filter out this noise, it is recommended that a 0.1 F
ceramic disc capacitor be placed between V
each device, with placement being as near to the device as
possible.
=
=
=
=
DATA IN
DATA IN
C
C
480mA
80 300 10
CC
L
L
STB
------------------------------------ -
V CC 80%
OE
dv dt
which could cause improper operation of the device.
tR tF
FIGURE 2. 82C86H/87H GATED INPUTS
–
12
CC
FIGURE 1. 82C82/83H
= 5.0V, C
5.0V 0.8
V
P
N
CC
V
P
N
CC
L
= 300pF on each eight out-
20 10
V
V
CC
CC
P
P
N
N
P
P
N
N
–
9
CC
and GND at
INTERNAL
DATA
INTERNAL
DATA
(EQ. 1)
(EQ. 2)
(EQ. 3)