LP3907SQ-JXQX NSC [National Semiconductor], LP3907SQ-JXQX Datasheet - Page 26

• Manufacturer Part Number: LP3907SQ-JXQX
• Description: Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface
• Manufacturer: NSC [National Semiconductor]

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I
I
The LP3907 features an I
two dedicated pins: SCL and SDA for I
spectively. Both signals need a pull-up resistor according to
the I
is clocked by the incoming SCL clock.
I
START and STOP bits classify the beginning and the end of
the I
transitioning from HIGH to LOW while the SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
2
2
2
C SIGNALS
C START AND STOP CONDITIONS
C Compatible Serial Interface
2
2
C session. START condition is defined as the SDA signal
C specification. The LP3907 interface is an I
2
C compatible serial interface, using
2
C clock and data re-
2
START and STOP Conditions
C slave that
I
2
C Signals: Data Validity
26
Signal timing specifications are according to the I
ification. The maximum bit rate is 400kbit/s. See I
cation from Philips for further details.
I
The data on the SDA line must be stable during the HIGH
period of the clock signal (SCL), e.g.- the state of the data line
can only be changed when CLK is LOW.
to HIGH while the SCL is HIGH. The
erates START and STOP bits. The I2C bus is considered to
be busy after START condition and free after STOP condition.
During data transmission, I
START conditions. First START and repeated START condi-
tions are equivalent, function-wise.
2
C DATA VALIDITY
30017816
30017817
2
C master can generate repeated
2
C master always gen-
2
C bus spec-
2
C specifi-