ST6200 STMICROELECTRONICS [STMicroelectronics], ST6200 Datasheet - Page 30

• Manufacturer Part Number: ST6200
• Description: 8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST6200C/ST6201C/ST6203C
5.11 REGISTER DESCRIPTION
INTERRUPT OPTION REGISTER (IOR)
Address: 0C8h — Write Only
Reset status: 00h
Caution: This register is write-only and cannot be
accessed by single-bit operations (SET, RES,
DEC,...).
Bit 7 =Reserved, must be cleared.
Bit 6 = LES Level/Edge Selection bit .
0: Falling edge sensitive mode is selected for inter-
Table 7. Interrupt Mapping
* Depending on device. See device summary on page 1.
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1
rupt vector #1
Vector #0
Vector #1
Vector #2
Vector #3
Vector #4
7
-
number
Vector
LES
Port A
Port B
TIMER
ESB
RESET
NMI
ADC *
Source
Block
GEN
Reset
Non Maskable Interrupt
Ext. Interrupt Port A
Ext. Interrupt Port B
Timer underflow
End Of Conversion
-
Description
-
NOT USED
-
0
-
Register
ADCR
TSCR
Label
N/A
N/A
N/A
N/A
1: Low level sensitive mode is selected for inter-
Bit 5 = ESB Edge Selection bit .
0: Falling edge mode on interrupt vector #2
1: Rising edge mode on interrupt vector #2
Bit 4 = GEN Global Enable Interrupt .
0: Disable all maskable interrupts
1: Enable all maskable interrupts
Note: When the GEN bit is cleared, the NMI inter-
rupt is active but cannot be used to exit from STOP
or WAIT modes.
Bits 3:0 = Reserved, must be cleared.
rupt vector #1
EOC
Flag
TMZ
N/A
N/A
N/A
N/A
STOP
from
Exit
yes
yes
yes
yes
yes
no
FFCh-FFDh
FFAh-FFBh
FFEh-FFFh
FF8h-FF9h
FF6h-FF7h
FF4h-FF5h
FF2h-FF3h
FF0h-FF1h
Address
Vector
Priority
Highest
Priority
Lowest
Priority
Order