BD37531FV-E2 ROHM [Rohm], BD37531FV-E2 Datasheet - Page 12

• Manufacturer Part Number: BD37531FV-E2
• Description: Sound Processors with Built-in 3-band Equalizer
• Manufacturer: ROHM [Rohm]

●Timming Chart
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CONTROL SIGNAL SPECIFICATION
(Unless specified particularly, Ta=25℃, VCC=8.5V)
* A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min. of the SCL
Table 1 Characteristics of the SDA and SCL bus lines for I
About 7(tHD;DAT), 8(tSU;DAT), make it the setup which a margin is fully in .
All values referred to VIH min. and VIL max. Levels (see Table 2).
1
2
3
4
5
6
7
8
9
(１) Electrical specifications and timing for bus lines and I/O stages
signal) in order to bridge the undefined region of the falling edge of SCL.
SDA
SCL
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time:
Data set-up time
Set-up time for STOP condition
P
t
BUF
S
t
HD;STA
t
LOW
Parameter
Fig.26
t
R
t
HD;DAT
Definition of timing on the I
t
HIGH
12/37
2
C-bus devices
t
F
t
SU;DAT
t
SU;STA
2
C-bus
Sr
tHD;STA
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
Symbol
ｆSCL
tHIGH
tBUF
tLOW
t
HD;STA
Fast-mode I
0.06*
Min.
1.3
0.6
1.3
0.6
0.6
120
0.6
0
t
t
SP
SU;STO
Technical Note
2010.03 - Rev.A
2
C-bus
Max.
400
－
－
－
－
－
－
－
－
P
Unit
kHz
μS
μS
μS
μS
μS
μS
μS
ns