LT4250H LINER [Linear Technology], LT4250H Datasheet - Page 10

• Manufacturer Part Number: LT4250H
• Description: Negative 48V Hot Swap Controller
• Manufacturer: LINER [Linear Technology]

APPLICATIONS
Figure 11. Undervoltage and Overvoltage Sensing
LT4250L/LT4250H
10
Undervoltage and Overvoltage Detection
The UV (Pin 3) and OV (Pin 2) pins can be used to detect
undervoltage and overvoltage conditions at the power
supply input. The UV and OV pins are internally connected
to analog comparators with 130mV and 20mV of hyster-
esis respectively. When the UV pin falls below its threshold
or the OV pin rises above its threshold, the GATE pin is
immediately pulled low. The GATE pin will be held low until
UV is high and OV is low.
The undervoltage and overvoltage trip voltages can be
programmed using a three resistor divider as shown in
Figure 11. With R4 = 549k, R5 = 6.49k and R6 = 10K, the
undervoltage threshold is set to 38.5V (with a 43V release
from undervoltage) and the overvoltage threshold is set to
71V. The resistor divider will also gain up the hysteresis
at the UV pin and OV pin to 4.5V and 1.2V at the input
respectively.
PWRGD/PWRGD Output
The PWRGD/PWRGD output can be used to directly en-
able a power module when the input voltage to the module
is within tolerance. The LT4250L has a PWRGD output for
modules with an active low enable input, and the LT4250H
has a PWRGD output for modules with an active high
enable input.
When the DRAIN voltage of the LT4250H is high with
respect to V
V
V
UV
OV
= 1.255
= 1.255
–48V RTN
R4 + R5+ R6
R4 + R5+ R6
(SHORT PIN)
R5 + R6
EE
–48V RTN
R6
– 48V
(Figure 12) or the GATE voltage is low, the
R4
R5
R6
U
INFORMATION
3
2
U
UV
OV
LT4250L/LT4250H
V
V
EE
DD
4
8
W
4250 F11
–48V RTN
(SHORT PIN)
– 48V
U
–48V RTN
* DIODES INC. SMAT70A
*
R4
R5
R6
3
2
UV
OV
LT4250H
internal transistor Q3 is turned off and I
PWRGD pin one SAT drop ( 0.3V) above the DRAIN pin.
Transistor Q2 sinks the module’s pull-up current and the
module turns off.
When the DRAIN voltage drops below V
voltage is high, Q3 will turn on, shorting the bottom of I
to DRAIN and turning Q2 off. The pull-up current in the
module pulls the PWRGD pin high and enables the
module.
When the DRAIN voltage of the LT4250L is high with
respect to V
down transistor Q2 is off and the PWRGD pin is in a high
impedance state (Figure 13). The PWRGD pin will be
pulled high by the module’s internal pull-up current source,
turning the module off. When the DRAIN voltage drops
below V
the PWRGD pin will pull low, enabling the module.
The PWRGD signal can also be used to turn on an LED or
optoisolator to indicate that the power is good as shown
in Figure 14.
Gate Pin Voltage Regulation
When the supply voltage to the chip is more than 20V, the
GATE pin voltage is regulated at 13.5V above V
voltage will be no greater than 18V for supply voltages up
to 80V.
V
GATE
–
+
V
GH
3
Figure 12. Active High Enable Module
+
–
GATE
V
4
1
EE
V
DL
DL
R1
and the GATE voltage is high, Q2 will turn on and
+
–
+
–
EE
SENSE
2
or the GATE voltage is low, the internal pull-
4
5
GATE
C1
6
V
I
DD
1
Q1
V
EE
Q3
R2
8
PWRGD
Q2
R3
DRAIN
C2
1
C3
7
1
and Q2 clamp the
DL
+
4250 F12
and the GATE
ENABLE MODULE
ACTIVE HIGH
V
EE
V
IN
ON/OFF
IN
+
–
. The gate
V
V
OUT
OUT
4250lhf
–
+
1