MCM63R836FC3.0 FREESCALE [Freescale Semiconductor, Inc], MCM63R836FC3.0 Datasheet - Page 13

• Manufacturer Part Number: MCM63R836FC3.0
• Description: MCM63R836
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

READ AND WRITE OPERATIONS
CK clock. These signals must meet the setup and hold times
shown in the AC Characteristics table. On the rising edge of
the following clock, read data is clocked into the output regis-
ter and available at the outputs at t KHQV . During this same
cycle a new read address can be applied to the address pins.
cycle. Read cycles may follow write cycles immediately.
on SS at the rising edge of the CK clock has its effect on the
output drivers after the next rising edge of the CK clock. SW
low deselects the output drivers immediately (on the same
cycle).
WRITE AND BYTE WRITE FUNCTIONS
to nine bits of the RAM I/O bus. In all cases, the timing
parameters described for synchronous write input (SW)
apply to each of the byte write enable inputs (SBa, SBb,
etc.).
This allows the system designer not interested in performing
byte writes to connect the byte enable inputs to active low
(V SS ). Reads of all bytes proceed normally and write cycles,
activated via a low on SW, and the rising edge of the CK
clock, write the entire RAM I/O width. This way the designer
is spared having to drive multiple write input buffer loads.
puts in conjunction with the synchronous write input (SW). It
is important to note that writing any one byte will inhibit a read
of all bytes at the current address. The RAM cannot simulta-
neously read one byte and write another at the same ad-
dress. A write cycle initiated with none of the byte write
enable inputs active is neither a read or a write. No write will
occur, but the outputs will be deselected as in a normal write
cycle.
MOTOROLA FAST SRAM
All control signals are registered on the rising edge of the
A deselect cycle (dead cycle) must occur prior to a write
SS and SW control output drive. Chip deselect via a high
Note that in the following discussion the term “byte” refers
Byte write enable inputs have no effect on read cycles.
Byte writes are performed using the byte write enable in-
FUNCTIONAL OPERATION
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LATE WRITE
clock and write data is sampled on the following rising edge.
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to assure coherent
operation. This occurs in all cases whether there is a byte
write or a full word is written.
PROGRAMMABLE IMPEDANCE OPERATION
ance by terminating the ZQ pin to V SS through a precision
resistor (RQ). The value of RQ is five times the output imped-
ance desired. For example, 250
impedance of 50 .
cycles.
ments and is binary. The binary impedance has 256 values
and therefore, there are no significant disturbances that
occur on the output because of this smooth update method.
cycles for the impedance to be completely updated. At re-
covery from sleep mode, the previously programmed value
will be recovered.
POWER UP AND INITIALIZATION
recommended: V SS , V DD , then V DDQ . Please note, per the
Absolute Maximum Ratings table, V DDQ is not to exceed
V DDQ + 0.5 V or 2.0 V max, whatever the instantaneous
value of V DD . Once supplies have reached specification
levels, a minimum dwell of 1.0 ms with CK clock inputs
cycling is required before beginning normal operations. At
power up the output impedance will be set at approximately
50
The write address is sampled on the first rising edge of
The late write feature is implemented with single stage
The designer can program the RAMs output buffer imped-
Impedance updates occur during write and deselect
The actual change in the impedance occurs in small incre-
At power up, the output impedance will take up to 65,000
The following supply voltage application sequence is
as stated above.
MCM63R836 MCM63R918
resistor will give an output
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