MCM63R836FC3.0 FREESCALE [Freescale Semiconductor, Inc], MCM63R836FC3.0 Datasheet - Page 16

• Manufacturer Part Number: MCM63R836FC3.0
• Description: MCM63R836
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MCM63R836 MCM63R918
16
TCK — TEST CLOCK (INPUT)
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS — TEST MODE SELECT (INPUT)
is the command input for the TAP controller state machine.
An undriven TMS input will produce the same result as a
logic 1 input level.
TDI — TEST DATA IN (INPUT)
the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is deter-
mined by the state of the TAP controller state machine and
the instruction that is currently loaded in the TAP instruction
register (see Figure 6). An undriven TDI pin will produce the
same result as a logic 1 input level.
TDO — TEST DATA OUT (OUTPUT)
state machine (see Figure 6). Output changes in response to
the falling edge of TCK. This is the output side of the serial
registers placed between TDI and TDO.
TRST — TAP RESET
IEEE 1149.1. The test–logic reset state is entered while TMS
is held high for five rising edges of TCK. Power on reset cir-
cuitry is included internally. This type of reset does not affect
the operation of the system logic. The reset affects test logic
only.
OVERVIEW
the sequences of 1s and 0s input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift regis-
ters that capture serial input data on the rising edge of TCK
and push serial data out on subsequent falling edge of TCK.
When a register is selected it is “placed” between the TDI
and TDO pins.
INSTRUCTION REGISTER
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are 3 bits long. The register can be loaded when it is placed
between the TDI and TDO pins. The instruction register is
automatically preloaded with the IDCODE instruction at pow-
er–up or whenever the controller is placed in test–logic–reset
state.
BYPASS REGISTER
placed between TDI and TDO. It allows serial test data to be
passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
Clocks all TAP events. All inputs are captured on the rising
The TMS input is sampled on the rising edge of TCK. This
The TDI input is sampled on the rising edge of TCK. This is
Output that is active depending on the state of the TAP
This device does not have a TRST pin. TRST is optional in
The various TAP registers are selected (one at a time) via
The instruction register holds the instructions that are
The bypass register is a single bit register that can be
TEST ACCESS PORT REGISTERS
TEST ACCESS PORT PINS
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BOUNDARY SCAN REGISTER
number of active input and I/O connections on the RAM (not
counting the TAP pins). This also includes a number of place
holder locations (always set to a logic 1) reserved for density
upgrade address pins. There are a total of 70 bits in the case
of the x36 device and 51 bits in the case of the x18 device.
The boundary scan register, under the control of the TAP
controller, is loaded with the contents of the RAMs I/O ring
when the controller is in capture–DR state and then is placed
between the TDI and TDO pins when the controller is moved
to shift–DR state. Several TAP instructions can be used to
activate the boundary scan register.
bump connects to each boundary scan register location. The
first column defines the bit’s position in the boundary scan
register. The shift register bit nearest TDO (i.e., first to be
shifted out) is defined as bit 1. The second column is the
name of the input or I/O at the bump and the third column is
the bump number.
IDENTIFICATION (ID) REGISTER
vice and vendor specific 32–bit code when the controller is
put in capture–DR state with the IDCODE command loaded
in the instruction register. The code is loaded from a 32–bit
on–chip ROM. It describes various attributes of the RAM as
indicated below. The register is then placed between the TDI
and TDO pins when the controller is moved into shift–DR
state. Bit 0 in the register is the LSB and the first to reach
TDO when shifting begins.
ID Register Presence Indicator
Motorola JEDEC ID Code (Compressed Format, per
IEEE Standard 1149.1 – 1990
Reserved For Future Use
Device Width
Device Depth
Revision Number
Bit No.
Bit No.
Value
Bit No.
The boundary scan register is identical in length to the
The Bump/Bit Scan Order tables describe which device
The ID register is a 32–bit register that is loaded with a de-
Value
Value
Configuration
Configuration
Bit No.
Value
256K x 36
512K x 18
256K x 36
512K x 18
11
0
Figure 5. ID Register Bit Meanings
31
0
1
x
10
17
x
0
Bit No.
Bit No.
9
0
Value
Value
Value
Value
30
x
16
x
8
0
7
0
MOTOROLA FAST SRAM
15
22
27
29
x
0
0
0
0
x
6
0
21
26
0
0
0
0
5
0
14
x
28
x
4
1
20
25
1
0
1
1
13
x
3
1
19
24
0
1
1
1
2
1
12
x
18
23
0
1
0
1
1
0