MC2GH256NMCA-2SA00 SAMSUNG [Samsung semiconductor], MC2GH256NMCA-2SA00 Datasheet - Page 44

• Manufacturer Part Number: MC2GH256NMCA-2SA00
• Description: SAMSUNG MultiMediaCard
• Manufacturer: SAMSUNG [Samsung semiconductor]

6.2.1 Command Sets And Extended Settings
The card operates in a given command set, by default, after a power cycle or reset by CMD0, it is the MultiMediaCard
standard command set, using a single data line, DAT0. The host can change the active command set by issuing the
SWITCH command (CMD6) with the ‘Command Set’ access mode selected.
The supported command sets, as well as the currently selected command set, are defined in the EXT_CSD register. The
EXT_CSD register is divided in two segments, a Properties segment and a Modes segment. The Properties segment con-
tains information about the card capabilities. The Modes segment reflects the current selected modes of the card.
The host reads the EXT_CSD register by issuing the SEND_EXT_CSD command. The card sends the EXT_CSD register
as a block of data, 512 bytes long. Any reserved, or write only field, reads as ‘0’.
The host can write the Modes segment of the EXT_CSD register by issuing a SWITCH command and setting one of the
access modes. All three modes access and modify one of the EXT_CSD bytes, the byte pointed by
The SWITCH command can be used either to write the EXT_CSD register or to change the command set. If the SWITCH
command is used to change the command set, the Index and Value field are ignored, and the EXT_CSD is not written. If
the SWITCH command is used to write the EXT_CSD register, the Cmd Set field is ignored, and the command set
remains unchanged.
The SWITCH command response is of type R1b, therefore, the host should read the card status, using SEND_STATUS
command, after the busy signal is de-asserted, to check the result of the SWITCH operation.
6.2.2 High Speed Mode Selection
After the host verifies that the card complies with version 4.0, or higher, of this standard, it has to enable the high speed
mode timing in the card, before changing the clock frequency to a frequency higher than 20MHz.
After power-on, or software reset, the interface timing of the card is set as specified in Table 5-7, Chapter 5. For the host to
change to a higher clock frequency, it has to enable the high speed interface timing. The host uses the SWITCH command
to write 0x01 to the HS_TIMING byte, in the Modes segment of the EXT_CSD register.
The valid values for this register are defined in ’HS_TIMING’, in page 37. If the host tries to write an invalid value, the
HS_TIMING byte is not changed, the high speed interface timing is not enabled, and the SWITCH_ERROR bit is set.
6.2.3 Power Class Selection
After the host verifies that the card complies with version 4.0, or higher, of this standard, it may change the power class of
the card.
After power-on, or software reset, the card power class is class 0, which is the default, minimum current consumption
class for the card type, either High Voltage or Dual voltage card. The PWR_CL_ff_vvv bytes, in the EXT_CSD register,
reflect the power consumption levels of the card, for a 4 bits bus, an 8 bit bus, at the supported clock frequencies (26MHZ
or 52MHz).
The host reads this information, using the SEND_EXT_CSD command, and determines if it will allow the card to use a
higher power class. If a power class change is needed, the host uses the SWITCH command to write the POWER_CLASS
byte, in the Modes segment of the EXT_CSD register.
The valid values for this register are defined in ’PWR_CL_ff_vvv’, in page 84 If the host tries to write an invalid value, the
POWER_CLASS byte is not changed and the SWITCH_ERROR bit is set.
1.The Index field can contain any value from 0-255, but only values 0-191 are valid values. If the Index value is in the 192-255 range
the card does not perform any modification and the SWITCH_ERROR status bit is set.
00
01
10
11
Revision 0.3
Access Bits
Command Set
Set Bits
Clear Bits
Write Byte
Access Name
The command set is changed according to the Cmd Set field of the argument
The bits in the pointed byte are set, according to the ‘1’ bits in the Value field.
The bits in the pointed byte are cleared, according to the ‘1’ bits in the Value field.
The Value field is written into the pointed byte.
Table 6-2 : EXT_CSD Access Modes
44
Operation
MultiMediaCard
the Index field
Sep.22.2005
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