ADN2873ACPZ-RL7 AD [Analog Devices], ADN2873ACPZ-RL7 Datasheet - Page 16

• Manufacturer Part Number: ADN2873ACPZ-RL7
• Description: 3.3 V, 50 Mbps to 4.25 Gbps, Single-Loop, Laser Diode Driver
• Manufacturer: AD [Analog Devices]

ADN2873
LOOP BANDWIDTH SELECTION
To ensure that the ADN2873 control loop has sufficient
bandwidth, the average power loop capacitor (PAVCAP) is
calculated using the slope efficiency of the laser (watts/amps)
and the average power required.
For resistor setpoint control,
For voltage setpoint control,
where:
LI is the typical slope efficiency at 25°C of a batch of lasers that
P
are used in a design (mW/mA).
LI can be calculated as
where:
P1 is the optical power (mW) at the one level.
P0 is the optical power (mW) at the zero level.
The capacitor value equation is used to obtain a centered value
for the particular type of laser that is used in a design and an
average power setting. The laser LI can vary by a factor of 7
between different physical lasers of the same type and across
temperatures without the need to recalculate the PAVCAP value.
This capacitor is placed between the PAVCAP pin and ground.
It is important that the capacitor is a low leakage, multilayer
ceramic type with an insulation resistance greater than 100 GΩ
or a time constant of 1000 sec, whichever is less. Pick a standard
off-the-shelf capacitor value such that the actual capacitance is
within ±30% of the calculated value after the capacitor’s own
tolerance is taken into account.
POWER CONSUMPTION
The ADN2873 die temperature must be kept below 125°C. The
LFCSP has an exposed paddle, which should be connected so
that it is at the same potential as the ADN2873 GND pins.
AV
is the average power required (mW).
PAVCAP
PAVCAP
LI
Figure 34. Recommended Method of I
=
P1
I
MOD
MICROCONVERTER
−
P0
=
=
Sense Resistor in Resistor Setting Mode
. 1
3
2 .
28
PHOTODIODE
×
×
10
10
INPUT
ADC
− 6
− 6
×
×
P
LI
P
AV
LI
AV
V
CC
R
MPD
PAVSET
ADN2873
Measurement Across a
(mW/mA)
(Farad)
(Farad)
Rev. 0 | Page 16 of 20
Power consumption can be calculated as
Thus, the maximum combination of I
calculated, where:
I
with I
T
V
V
V
T
AUTOMATIC LASER SHUTDOWN (T
ALS (T
optical output of the transmitter. The ALS pin is pulled up
internally with a 6 kΩ resistor and conforms to SFP MSA
specifications. When ALS is logic high or when open, both the
bias and modulation currents are turned off. If an alarm has
been triggered and the bias and modulation currents are turned
off, ALS can be brought high and then low to clear the alarm.
BIAS AND MODULATION MONITOR CURRENTS
IBMON and IMMON are current-controlled current sources
that mirror a ratio of the bias and modulation current. The
monitor bias current, IBMON, and the monitor modulation
current, IMMON, should both be connected to ground through
a resistor to provide a voltage proportional to the bias current
and modulation current, respectively. When using a micro-
controller, the voltage developed across these resistors can be
connected to two of the ADC channels, making a digital
representation of the bias and modulation current available.
IBIAS PIN
The ADN2873 IBIAS pin has one on-chip, 800 Ω pull-up resistor.
The current sink from this resistor is V
where V
of one laser bias current, I
Usually, when set up, a maximum laser bias current of 100 mA
results in a V
3.6 V, V
resistor) ≤ 3 mA.
This on-chip resistor damps out the low frequency oscillation
observed from some inexpensive lasers. If the on-chip resistance
does not provide enough damping, one external R
may be necessary.
CC
DIE
AMBIENT
BIAS_PIN
MODP_PIN
MODN_PIN
min = 32 mA, the typical value of I
is the die temperature.
I
P = V
T
I
CC
BIAS
DIE
UP
X
IBIAS
= I
is the voltage at the IBIAS pin.
is the ambient temperature.
IBIAS
_DISABLE) is an input that is used to shut down the
= T
is the voltage at the IMODP pin.
=
= I
is the voltage at the IMODN pin.
CC
CC
= 1.2 V, and I
V
× I
MOD
is the voltage measured at the IBIAS pin after setup
AMBIENT
CC
IBIAS
min + 0.3 I
CC
−
0
= 0.
8 .
to about 1.2 V. In a worst-case scenario, V
+ ( I
V
IBIAS
+ θ
BIAS
JA
UP
× V
MOD
× P
BIAS
(the current bypass through the 800 Ω
BIAS_PIN
.
) + I
MOD
BIAS
CC
IBIAS
provided in Table 1
( V
+ I
dependent.
MODP_PIN
MOD
X
_DISABLE)
Z
must be
(see Figure 35)
+ V
MODN_PIN
(mA)
CC
)/2
=