AD5415YRU-REEL AD [Analog Devices], AD5415YRU-REEL Datasheet - Page 5

• Manufacturer Part Number: AD5415YRU-REEL
• Description: Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface
• Manufacturer: AD [Analog Devices]

TIMING CHARACTERISTICS
Temperature range for Y Version: −40°C to +125°C. See Figure 2 and Figure 3.
Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
V
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
1
2
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
Falling or rising edge as determined by the control bits of serial word. Strong or weak SDO driver selected via the control register.
Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with a load circuit, as shown in
DD
2
= 2.5 V to 5.5 V, V
LDAC
LDAC
SYNC
SCLK
DIN
1
2
Limit at T
50
20
8
8
13
5
4
5
30
0
12
10
25
60
REF
= 5 V, I
t
8
MIN
NOTES
1
2
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.
ASYNCHRONOUS LDAC UPDATE MODE
SYNCHRONOUS LDAC UPDATE MODE
t
OUT
, T
4
DB15
MAX
2 = 0 V. All specifications T
t
5
t
6
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Figure 2. Standalone Mode Timing Diagram
t
2
Rev. 0 | Page 5 of 28
MIN
t
1
DD
to T
Conditions/Comments
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK falling edge
Minimum SYNC high time
SCLK falling edge to LDAC falling edge
LDAC pulse width
SCLK falling edge to LDAC rising edge
SCLK active edge to SDO valid, strong SDO driver
SCLK active edge to SDO valid, weak SDO driver
t
3
) and timed from a voltage level of (V
MAX
DB0
, unless otherwise noted.
t
7
t
9
t
10
t
11
1
IL
+ V
IH
)/2.
Figure 4
AD5415
.